Is there any standard package that can convert TRUE to '1' and FALSE to '0'? Should I write my function? Why there isn't implicit sythax of that?
- posted
20 years ago
Is there any standard package that can convert TRUE to '1' and FALSE to '0'? Should I write my function? Why there isn't implicit sythax of that?
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:Is there any standard package that can convert TRUE to '1' and FALSE to '0'? :Should I write my function? Why there isn't implicit sythax of that? :
There are a number of standard functions for this, in the various libraries. Example: ieee.numeric_extra.to_std_logic()
There isn't "implicit syntax" because VHDL is a strongly-typed language. You can only change one type to another explicitly. (Some day, that will save your life :)
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