I have a DCM that drives a 1X clock and 2X clock on BUFGs. In one case, the enable to a CLK2X register depends on a CLK1X based FF. Looking at the path delays, there is no problem with setup and hold, but the timing analyzer reports a hold violation that is essentially the actual path delay plus the CLK2X period. The required hold time is
0ns. Is there any way around this, or should I just ignore the error? I don't think that it should be showing a half cycle of skew between two non-phase-shifted clocks. For some reason, the 2X versus 1X seems to be confusing it.Chris