Block RAM vs Flip Flop

In the following (use a font with fixed width to display it rightly)

+-------------/--------+ | 32 | | ___ | +----| \ | | | __ | __ > + |-----| | | data_in---| | | | | |---+---data_out | |-----/----|___/ +-->__| clk-->__| 32 ADD | XX FD | clk

when XX = 32 FD: Timing Summary:

--------------- Speed Grade: -4 Minimum period: 5.938ns (Maximum Frequency: 168.407MHz) Minimum input arrival time before clock: 1.825ns Maximum output required time after clock: 7.241ns Maximum combinational path delay: No path found

when XX = RAMB16_S36 with WE => '1' ,SSR => '0' : Timing Summary:

--------------- Speed Grade: -4 Minimum period: No path found Minimum input arrival time before clock: 1.825ns Maximum output required time after clock: No path found Maximum combinational path delay: No path found

Does "Minimum period: No path found" here suggest that is good idea to not use only RamBlock as sequential element in spite of it's clock signal?

If Yes... is good to use a RamBlock and, after it, 32 transparent latch or is better to use RamBlock and, after it, 32 flipflop ?

Regards Sandro

Reply to
Sandro
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Sandro schrieb:

I dont understand this sentence.

BRAMS are slower than FlipFlops. But in your sentence I guess the tool "see" that the adress bus is static and do some optimizations (remove the BRAMs?), that why no minimum period is found. Usually to speed up BRAM operation inputs and outputs are registered be fabric FlipFlops.

Regards Falk

Reply to
Falk Brunner

sorry for my ugly english...

Don't seems XST remove the BRAM... and the address bus is not static (I done some trial with 32 flip flop after seeing the ?problem? with ram block) :

Device utilization summary:

--------------------------- Selected Device : 3s200ft256-4 Number of Slices: 34 out of 1920 1% Number of 4 input LUTs: 32 out of 3840 0% Number of IOs: 75 Number of bonded IOBs: 74 out of 173 42% IOB Flip Flops: 32 Number of BRAMs: 1 out of 12 8% Number of GCLKs: 1 out of 8 12%

bye Sandro

Reply to
Sandro

Sandro schrieb:

Ok, but IOB FlipFlops are not optimal for this test, since the are located "far" away from the BRAMs. You should disable the option for using IOB FlipFlops. Look at the timing report, this shoudl give you some hints for the missing minimum period.

Regards Falk

Reply to
Falk Brunner

1) the 32 IOB FLipFlop here are for one input to the adder... the other input of the adder is only from the BRAM 2) Disabling the "Pack I/O Registers/Latches into IOBs" is a MAP option... the report report is a XST report.

Sandro

Reply to
Sandro

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