I am getting a strange error with Block RAM on a Spartan 3 FPGA. Every time I issue a read, the word at the location previous to the given address is read. For example if I'm reading from address 5, the word at address 4 is output instead. The data written to the block seems correct when I view it in ModelSim so I assume it's something with the read.
Viewing signals at the BRAM input in ModelSim shows the correct address at the input of port A and the read clock signal goes high but the wrong word appear at the output. ENA is always 1 and WEA is always
- The very most recent Write to this same address (from a different port) also shows the correct value being written.
The design works correctly in RTL but this problem only occurs with the post-route netlist.
Did anyone encounter a similar problem like this before and can give me a hint on what's going on.
Thank you.