I am doing a project for a Virtex2 fpga with the Free ISE WebPACK 5.2i with all the latest patches. I am writing a piece of behavioral VHDL that will synthesize as dual ported block ram and a testbench to verify its behavior by writing three values to it and then read them back. This works all fine in a behavioral simulation, but when I advance to a post-translate or post-place & route simulation the last of the three values read ( the first written) is wrong. Can someone tell me what is wrong? Maybe it is never written?
I have also tried to instantiate the block ram manualy (RAMB1_s36_s36). This gives exactly the same problem.
Sincerely Christian.
This is my VHDL
----Memory.vhd------------------ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity memory is Port ( clk : in std_logic; reset : in std_logic; write_addr : in std_logic_vector(8 downto 0); write_data : in std_logic_vector(31 downto 0); write_en : in std_logic; read_addr : in std_logic_vector(8 downto 0); read_data : out std_logic_vector(31 downto 0); read_en : in std_logic); end memory;
architecture Behavioral of memory is type mem_type is array (511 downto 0) of std_logic_vector(31 downto 0); signal data : mem_type := (OTHERS => (OTHERS => '0')); begin process (clk) begin IF clk'event AND clk = '1' then if write_en = '1' then data(CONV_INTEGER(UNSIGNED(write_addr))) reset, write_addr => write_addr, write_data => write_data, write_en => write_en, read_addr => read_addr, read_data => read_data, read_en => read_en );
PROCESS BEGIN clk