Hi again,
What does the setting of the attribute box_type to "black_box" for my toplevel components effect (concerning modular design flow)?
Syntax checking in ISE projnav searchs for the components' modules anyway, whether black boxed or not.
greetings
Hello,
Maybe I don't have enough background, but I have a ISE project with several black-boxed components instantiated in my toplevel design. This toplevel vhdl-module was generated by the EDK. Now I have the problem, that XST throws errors, when I try to check the syntax, because it can't find the instantiated modules, even they are marked black boxed. So I added the concerning wrapper vhdl-sources also generated by the EDK to the ISE project. But now I run in a kind of recursion, because these wrapper modules use several library modules themselves, that are unknown to the ISE.
Why does the ISE even look inside the wrapper modules, when it shouldn't take care for their implementation at all, because of the "black_box"-ing. Did I get you wrong?
thanks
Paulo Dutra schrieb:
Sorry, I don't know much about the check syntax function.
I think what you describe is a concern. The "box_type" attributes are synthesis directives that only XST understands when it parses/analyzes HDL files. Given that the check syntax function doesn't understand XST attributes, then it will flag an error for components that do not have an associated entity declaration.
You have the correct line of thinking by including wrapper modules. But, this will get into trouble as you outlined. What's needed here are wrapper modules that declare blackbox entity declarations.
For your situation, you would have to bypass the check syntax. The HDL is still correct for synthesis.
L. Schreiber wrote:
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