We are using VHDL on a new design with a Lattice 4256V and are running into problems with our shift registers. We're using ispLEVER 5.1 trial along with Synplicity synthesis. Here's our generic 11-bit shift register with async. parallel load:
--
-- 11 bit shifter for data serialization
-- library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_arith.all; use IEEE.STD_LOGIC_unsigned.all;
entity shifter11 is port( clk:in std_logic; rst:in std_logic; data_in:in std_logic_vector(10 downto 0); shift_load_select:in std_logic; shift_in:in std_logic; data_out:out std_logic); end shifter11;
architecture bhv of shifter11 is signal data_latched: std_logic_vector(10 downto 0); begin process(clk,rst,data_in,shift_load_select) begin if(rst='0') then data_latched