Hi All,
Does anyone have any experience with getting their bit order reversed in Xilinx post-translate simulation? I am using Xilinx ISE ver 8.2.03i and ModelSim III XE 6.1e starter edition, and this mysteriously started happening to me last week when I never had a problem with this before. I have reinstalled both programs and have reverted to testing only what Xilinx gives me, and I still get the problem. I generated user_logic.vhd by following the directions in the EDK_82_PPC_Tutorial.pdf for the ML403 board; see
With fresh installs of ISE and ModelSim, no changes to Synthesize or Translate options, no touching of any ModelSim menu options, and VHDL straight out of Xilinx's own user_logic from the Create Peripheral Wizard that always worked before (and works in Behavioral sim), what is left? What could I have set generally on my computer that could be causing this? Could there be some Translate option that I idiotically set and didn't remember that I set?
It must be a problem with how ISE creates models for simulation, or in the simulator, since I can put my built project in the ML403 board and write and read the slv_regs correctly following the tutorial, over RS232. However, my core doesn't seem to be giving the correct output, so I need to simulate, and therefore I need a reliable simulation process.
Thanks in advance,
-James
Here's user_logic.vhd as I am simulating it (straight from the Create Peripheral Wizard, with only the two "library proc_common_v2_00_a" lines commented-out so that the syntax check will succeed -- this always worked before):
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Tue Oct 03 15:53:39 2006 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "I_"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE -------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;
--library proc_common_v2_00_a;
--use proc_common_v2_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_DWIDTH -- User logic data bus width
-- C_NUM_CE -- User logic chip enable bus width
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus for user logic
-- Bus2IP_BE -- Bus to IP byte enables for user logic
-- Bus2IP_RdCE -- Bus to IP read chip enable for user logic
-- Bus2IP_WrCE -- Bus to IP write chip enable for user logic
-- IP2Bus_Data -- IP to Bus data bus for user logic
-- IP2Bus_Ack -- IP to Bus acknowledgement
-- IP2Bus_Retry -- IP to Bus retry response
-- IP2Bus_Error -- IP to Bus error response
-- IP2Bus_ToutSup -- IP to Bus timeout suppress
------------------------------------------------------------------------------
entity user_logic is generic ( -- ADD USER GENERICS BELOW THIS LINE --------------- --USER generics added here -- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol parameters, do not add to or delete C_DWIDTH : integer := 32; C_NUM_CE : integer := 4 -- DO NOT EDIT ABOVE THIS LINE --------------------- ); port ( -- ADD USER PORTS BELOW THIS LINE ------------------ --USER ports added here -- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol ports, do not add to or delete Bus2IP_Clk : in std_logic; Bus2IP_Reset : in std_logic; Bus2IP_Data : in std_logic_vector(0 to C_DWIDTH-1); Bus2IP_BE : in std_logic_vector(0 to C_DWIDTH/8-1); Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_CE-1); Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_CE-1); IP2Bus_Data : out std_logic_vector(0 to C_DWIDTH-1); IP2Bus_Ack : out std_logic; IP2Bus_Retry : out std_logic; IP2Bus_Error : out std_logic; IP2Bus_ToutSup : out std_logic -- DO NOT EDIT ABOVE THIS LINE --------------------- ); end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
------------------------------------------ -- Signals for user logic slave model s/w accessible register example ------------------------------------------ signal slv_reg0 : std_logic_vector(0 to C_DWIDTH-1); signal slv_reg1 : std_logic_vector(0 to C_DWIDTH-1); signal slv_reg2 : std_logic_vector(0 to C_DWIDTH-1); signal slv_reg3 : std_logic_vector(0 to C_DWIDTH-1); signal slv_reg_write_select : std_logic_vector(0 to 3); signal slv_reg_read_select : std_logic_vector(0 to 3); signal slv_ip2bus_data : std_logic_vector(0 to C_DWIDTH-1); signal slv_read_ack : std_logic; signal slv_write_ack : std_logic;
begin
--USER logic implementation added here
------------------------------------------ -- Example code to read/write user logic slave model s/w accessible registers -- -- Note: -- The example code presented here is to show you one way of reading/writing -- software accessible registers implemented in the user logic slave model. -- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond -- to one software accessible register by the top level template. For example, -- if you have four 32 bit software accessible registers in the user logic, you -- are basically operating on the following memory mapped registers: -- -- Bus2IP_WrCE or Memory Mapped -- Bus2IP_RdCE Register -- "1000" C_BASEADDR + 0x0 -- "0100" C_BASEADDR + 0x4 -- "0010" C_BASEADDR + 0x8 -- "0001" C_BASEADDR + 0xC -- ------------------------------------------ slv_reg_write_select