.bit file to VHDL/verilog source code

I am currently working on an old board which have eight FPGA XC3130 on board and i dont have a source code for those FPGA's except for .bit file which was downloaded through VME bus.

Currently i am redesigning the board eliminating all the PAL's on the board with high end FPGA and also want to incorporate the obsolescence XC3130 into them.But i dont have a source code except for .BIT (Bitstream)file.

Is there any software which could convert the .bit file to VHDL/ Verilog?or even a functional block?

Any alternative suggestions to go ahead with this board redesign ?

Thank you Naveen

Reply to
lingamaneni.naveen
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I am currently working on an old board which have eight FPGA XC3130 on board and i dont have a source code for those FPGA's except for .bit file which was downloaded through VME bus.

Currently i am redesigning the board eliminating all the PAL's on the board with high end FPGA and also want to incorporate the obsolescence XC3130 into them.But i dont have a source code except for .BIT (Bitstream)file.

Is there any software which could convert the .bit file to VHDL/ Verilog?or even a functional block?

Any alternative suggestions to go ahead with this board redesign ?

Thank you Naveen

Reply to
lingamaneni.naveen

With or without comments?

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, 
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266
Reply to
Mark McDougall

LOL.

Reverse engineering is generally very difficult, but it could perhaps be possible to extract the netlist, i.e. the low-level connections between the individual registers, LUTs, etc. Not that I have the skill/time/knowledge, but perhaps someone else has already done something similar.

Whether that is of any use for the OP is unknown to me.

-Michael.

Reply to
Michael Jørgensen

Oh. That would be *nasty*.

JB

Reply to
jbnote

If you were analyzing a newer part, you could make use of 'debit', a tool available from

formatting link

I have only given it a cursory look, but it appears to reverse a bitstream into a custom textual netlist. So additional work would be required to take it to EDIF, XDL, or the like. But it does draw pretty fpga_editor-like pictures from bitstreams.

Stephen

Reply to
stephen.craven

The link appears broken (Page not found), and the home page only displays "It works". Are you sure the link is correct?

-Michael.

Reply to
Michael Jørgensen

I've taken the website down. I was not expecting the link to be spread. I'll do an announcement here when i'm ready for public release.

JB

Reply to
jbnote

On the other hand, the older parts were smaller. Maybe small enough that it could be done partly by hand. If you had some idea what the logic was supposed to do, that would help.

-- glen

Reply to
glen herrmannsfeldt

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