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Bidirectional signals with Altera Signaltap

Dear all, I am trying to using SignalTap to debug a design in which I have some bidirectional ports. Using both Pre-synthesis and Post-fitting (while using incremental routing) Signal-Tap signals I am not able to find the IO port in order to include it in the acquisition. I tried to find some answer in Altera website or in the manual but I found nowhere any reference to bidirectional ports and signaltap. Is it a limitation of the software? Is there a way to overcome it? Apart from introducing two more Input and Output port for watching the signal in both phases?

Thank you all

Guido

Reply to
Guido
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Hello Guido,

A short piece od HDL is shown below to explain this: module simple_bidir( clk, oe, bidir_pin, in_pin, out_pin );

input clk;

inout bidir_pin;

input oe;

input in_pin;

output out_pin;

reg in_reg, out_reg;

assign bidir_pin = oe ? in_reg : 1'bZ ;

always @ (posedge clk)

begin

in_reg found nowhere any reference to bidirectional ports and signaltap.

Reply to
Subroto Datta

Thank you very much for your useful tips!

Guido

Reply to
Guido

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