bidirectional pin help

Try grounding this pin through a let's say 5K resistor and see if it will still be at 5V.

Your synthesizer might not be recognizing a bidirectional signal properly because you mixed it up with other stuff in the same process. In my experience it is better to code such things separately following templates precisely:

Thanks for Your answer Mikhail.

I am using Altera FPGA. When I compile my design I actualy get waring that my pin is constantly have Vcc value. When my pin works in output mode it should have Vcc value on the output, but I am not shure obout this High impedanse. I understood what You said to me, but I don't think that this is problem. I try something with 1M resistor and this voltage doesn't falling.

process (, )

I understand this code but I have one question if you could answer me. How can I read value that is in bidir pin when it is input. OK, you put it in High impedanse, it is clear. All I do in next few steps is reading this input value. Did You think that in this process I read this value and put it in some temporary value and that value to use in other process or what? That wasn't very clear to me.

I want to thank You again for Your try to help me, Mikhail Zoran

Zorjak,

I agree with MM, having the input and output behavior in the same process is confusing. Try something like this:

en_count

Thanks for Your try to help, Jeff,

I'll try to use input and output behavioral in diferent process. But, a few minutes ago I noticed something else in my work

You se that I have one output pin called "test". It has only one driving 'Z' (end of the process). But in my compilaton report I have the same waring as with bidir pin. (Pin test has Vcc driving its datain port). It's like that there is no problem if the pin is biderctional or not. It is something with this "High Impedanse" as I seee it. I am not shure about anything.

Library Ieee; Use ieee.std_logic_1164.all; Use Ieee.std_logic_arith.all; Use ieee.std_logic_unsigned.all; Library work;

-------------------------------------------------------------------------------- entity io_test_contr is port( con, clk : in std_logic; en_count : out std_logic; bidi : inout std_logic; test : out std_logic ); end io_test_contr;

-------------------------------------------------------------------------------- architecture io_test_contr_behav of io_test_contr is

signal temp : std_logic;

begin

process(con, bidi) begin if con='1' then bidi en_count

Here's a related example:

-- Mike Treseler

thanks ofr this links, Mike

I'll shurly see it

Thanks aga> Zorjak wrote:

Move your test

Thanks for all Your try to help Mikhail.

I contacted Altera suport (I use their FPGA) and they tell me this

------------------------------------------------------------------------------------------------------ I have compiled your design here on my computer and yes I also got the message

Info: Pin test has VCC driving its datain port

Regarding this message, the fact is that an open-drain buffer is implemented in the "test" I/O Buffer, as you can find on the "Output Pins" page under the "Resource Section" of the "Fitter" report in the Compilation Report window (Processing menu). The function of the open- drain buffer is that when its input is 0, output is 0; when its input is 1, output is high impedance. That's the reason why the datain port of the "test" pin is driven by VCC.

Regarding the 5V voltage measurement result, generally when a signal is in the high impedance state, there is still possibility that you can probe out a high level voltage, although there is no or little current strength on the signal. To confirm it is a high impedance state, please connect the probe to GND through a resistor while monitoring the signal. If a low logic level is monitored, it can be demonstrated that the signal is in high-Z state actually.

Please let me know if you have further questions on it.

I try to conect this pin with ground throght resistor and it work just as he said. But this doesn't solve problem to me. Do you maybe know, is there posibility that when I have high impedance on output I have

0V on it. i read something about open drain and open source on net but I didn't understood this very well. I have to look it a lot more.

Anyway, I want to thank for all Your try to help. Thanks again, Mikhail Zoran

I can't see how one can measure 5V on an open drain output without a pullup resistor... Why is it 5V anyways? What kind of FPGA are you using? All of the modern FPGA use lower voltages...

Also, any unused pin should be tristated on your FPGA, so see what you will measure on unused pins... Then do what I said about taking the test signal assignment out of the process.

/Mikhail

Mikhail,

I am using cyclone ep1c6q240c8 (UP3-1c6 development kit) I don't know too, how can I can measure 5V. How much I understand this FPGA it should work on 3.3V. That confused me to. I have mesured unused pins voltage (Yes, they are defined as input 3 stated) and I have also got 5V. I am totaly confused about all of this.

I have tried to put test signal out of pocess statement and nothing. Same waring, same measure result. "pin testhas Vcc driving his datain port".

Thanks again for Your try to help. I don't know what to say more:):) Zoran

OK, something is seriously wrong here. Let's start with your multimeter. Have you verified that it actually works? Try measuring power supplies on your board. Sorry if this will insult you, but make sure that while one of your probes touches the FPGA pin , another is at the board's ground.

/Mikhail

:):) You didn't insult me, Mikhail

My multimetar works fine, I am positive about that, I measure some other things with it and it is ok. And, Yes when I measure the voltage on FPGA pin another probe touch ground. I am 100% shure. Maybe, somewhere on the board is 3.3V to 5.V converter, I didn't pay much attention about that. I'll have to look about that Although this thing obout this board and fpga is confusing, I have more wories about this warring that I am getting from the quartus. It clearly says that this pin constantly geting Vcc on it. I could bet that this is some problem, not on the board. Mybe on the fpga is some pull up resistor and it can't be turned off. I don't know what else could be.

Thanks again Zoran

Zoran,

I have looked at the board's schematics. There are tons of pullups to 5V, so you probably are using one of these pins. How have you chosen your pins if you have chosen them at all?

With regards to what Quartus says, I haven't touched Altera for quite a number of years now, so I am not an expert here... Perhaps someone else would be better equipped to answer why it is using open-drain output and what exactly the warning means...

/Mikhail

Actually after having read the warning one more time and having re-read what Altera tech support guy told you I think I now understand what it all means. VCC doesn't mean VCC, it means logic '1', and it is not applied to the pin itself, it is applied to the datain port of the IO buffer, which happens to be an open-drain buffer, and an Altera open-drain buffer when fed logic '1' will have a transistor closed resulting high-impedance. So, I think everything works as it should and the 5V measured results from an external pullup resistor. Just study your schematics...

/Mikhail

I thinks something is finaly clear to me:). You must be right. I mean, it has to be it. When I was chosing my pins I didn't py much attention about that. Actualy I just piked the first from one of this conectors. I am now seeing this board and I am not shure how to eliminate this pull up, if there is any chance to eliminate it. But now, I am almost

100% shure that this has to be it and nothing else.

Mikhail, Your help was raly great, and I can't say You, how much I am thankful for all. Zoran

MM wrote: