Hi, I start work on some project involving FPGA and I have to define port as bidirectional (inut-output). I know that in VHDL there is keyword "inout" when defining port, but I don't know what detirminats that this kind defined port would be input or output.
If this is for a half-duplex bus application, I think it is prefered to have two signals, one input and one output and to combine them at the top level with the appropriate buffers, instead of a single input/output signal. That way, it is clear what is being sent out and that is being brought in. If the inout is just so you can read a value that you are outputting, then it is best to use an internal signal that holds the value to output. This means that you can both drive a value on the line and read the value at the same time.
But, I am not shure that I understood You well. How did You mean to combine input and output signal? I need one pin that in one moment sends high voltage on the output, and in the time that follows it reads the input from the same wire. I never used this method so I am very confused.
Thanks aga> If this is for a half-duplex bus application, I think it is prefered to have
If that's what you need, just use the method that uses an internal signal tha hold the value that you want to output. Drive the output directly from the internal signal. You can also read the internal signal to see what value is driving the output.
The code snippet below gives an example of the above. This achieves the same effect as using an inout signal.
port(... output : out std_logic; ... );
signal outValue : std_logic;
...
begin ... process(clk)begin if(clk'event and clk = '1')then if(outValue = '0')then ... end if; end if; end process; ... output Thanks for Your answer, Matthew
Physically, a bidirectional port is a device with three internal connections - 'in', 'out' and 'oe'.
When 'oe' is active, the value of 'out' is driven on the pin, otherwise the output driver is off. At any time, you can read the current pin value on the 'in' signal.
When you drive the pin, you read back the value you are driving (output mode), when you are not driving the pin, you read back the pin state as determined by external circuitry.
In VHDL, if you set the signal value to 'Z', you disable the output driver. At that point you can read the external value from the signal.
It is common to map the VHDL inout signal into the three separate signals somewhere at the top of your VHDL hierarchy, as Mathew and Jeff have pointed out.
I agree with Jeff and Iwo, see Jeff's code above. One thing that I would add is when the signal value is set to 'Z' it means 'High impedance mode' - you are not driving that pin from inside the FPGA in that case, but rather you are able to sense what signal is coming to that pin from the outside towards the inside of the FPGA.
If it's an in-out port, you have to have at least one driver (a signal assignment statement). When you want the port to be an input, assign the std_logic value 'Z' to it.
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