Hi ,
Is it possible to implement signal declared as bidirectional (i.e.,inout) in FPGA.For example i have to declare bidirectional data bus D[7:0].should i use as two separate unidirectional?
regards, fazal
Hi ,
Is it possible to implement signal declared as bidirectional (i.e.,inout) in FPGA.For example i have to declare bidirectional data bus D[7:0].should i use as two separate unidirectional?
regards, fazal
Fazal, Are you a student or what ? There must be some one around you to reply to your queries. And keep one thing in mind: always study some text book before posting a question.
I cannot understand why some one is willing to make himself a "Butt of ridicule" in each and every of his post.
/Eldon
It is possible. In sub-modules, I prefer to use seperate input and output signals. At the top level, I use the language's bidirectional signal type and drive it with a value when output is enabled and with z's when the output isn't. The bidirectional port always drives the input set of signals. Synthesis tools will implement this however is best for your partcular device.
---Matthew Hicks
Synthesis
Thanks for your suggestions..
data
Here I give you an advice. Read the related FPGA datasheets then you wil know what there are in a FPGA. It is the resources in a FPGA determin what function a FPGA can implement.
Best regards
Leon,
Not exactly...
You can code a bidirectional tri-state bus for most synthesis tools, and when targeting devices without that capability, they will convert it to multiplexers.
That said, unidirectional tri-state bus descriptions have some particular advantages when dealing with mutual exclusiveness of the select lines. Synthesis assumes that tri-state enables on a bus are mutually exclusive, whereas coding a non-priority multiplexer with separate enable bits is sometimes difficult. But bidirectional internal signals are almost always better when implemented as separate unidirectional buses, tri-state or not.
Andy
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