Hello, I am using an Altera MAX3000A CPLD to make level conversion from 5V-TTL to
3.3V-TTL (and further jobs...). My problem is - I can't connect two bidirectional ports directly to get a bidirectional connection. I'm using Altera Quartus II, a direct connection produces an error message and a simple VHDL-block doesn't solve the problem, too. my VHDL-code is like: ENTITY ... port1 : INOUT STD_LOGIC; port2 : INOUT STD_LOGIC; ARCHITECTURE... port1Manfred Balik schrieb:
it's not possible. it would require an analog switching element being used to connect those 2 io pins.
depending on the protocol that is used there may or may not be a solution that can be implemented in full digitial domain.
Antti
You need to put a bit more thought into what it is that you're really trying to do. Let's say your code compiled and you now wanted to instantate the component somewhere. That code would look like this...
U1 : entity work.Mans_Entity port map( port1 => Sig1, port2 => Sig2);
Where 'Sig1' and 'Sig2' are the 'two' busses or signals that you're trying to connect. But in your code you implied (to me) that you'd like to take whatever comes in on either port and map it over to the other....which would then mean that logically 'Sig1' and 'Sig2' are the same thing and not separate things (i.e. one is the 5V side, the other is the 3.3V side)....which is a contradiction...which fundamentally is why what you have isn't working.
What you probably need to add is the concept of an output enable for both port1 and port2 and only drive the outputs when that output is enabled...
port1
KJ schrieb:
KJ
bidir connections between to io's are sometimes possible also when no enable signal exists, see NXP's I2C extender as one example
Antti
Yes, and an even simpler example of a bi-directional connection between two I/Os with no enable or direction signal is a resistor.
Since I wasn't quite sure exactly what the original poster was trying to do, I mentioned "What you probably need...." on the assumption that he is trying to come up with synthesizable code targetting some FPGA/CPLD or such (in which case I believe he will be needing the enable).
If instead the poster was interested in a non-synthesizable simulation model that connects two things bi-directionally without a 'direction' or 'enable' signal (i.e. like a resistor or the part you linked) than he will be wanting a different code entirely.
KJ
Thanks to KJ and Antti for your prompt answers!!!
I see - I will need a enable signal for each direction, because I want a synthesizable code not a simulation (I thought this is easy, just a connection :-( ).
the PCA9515 is a really nice bidirectional level converter, but I think he has a enable signal, too. Not a external direction signal, but internally generated out of weak low (the output of the PCA9515) and hard low (if the input is low).
Manfred
"KJ" schrieb im Newsbeitrag news: snipped-for-privacy@b28g2000cwb.googlegroups.com...
Manfred Balik schrieb:
the PCA9515 was just an example reference. it is not generic bidir buffer - such thing is not possible by definition. PCA9515 is somwehat 'protocol aware' and can be used as if it would be transparent bidir buffer for the constrained use of the I2C bus.
sometimes similar bidirectional buffer is possible to be implemented in PLD or FPGA or MCU also, but it always needs some 'protocol awareness' and some timing reference to avoid self-lockup.
Antti
Manfred Balik schrieb:
Actually you only need a direction signal if it is ok that one side is allways enabled. Make sure that all external drivers on a signal are enable when the CPLD is driving the signal.
As a side note: You probably do not need a level converter at all.
3.3V TTL outputs are fully 5V TTL compliant because 5V TTL only requires the outputs to be driven to 2.4V. You only need protection against 5V signals damaging the 3.3V device. If the signals are driven by real TTL logic that means that in many cases you need no protection at all because TTL drivers are very week above 3.3V. In other cases a series resistor will do the job.Kolja Sulimma
I changed my design to (like Antti suggested): port1 > >> no enable signal exists, see NXP's I2C extender as one example
When setting for example port1_output_enable='1' and port2_output_enable/='1', something else should drive port2. Either your testbench or another part of the design. This driver should be tri-stated if port2_output_enable='1' and driven by some source if port2_output_enable/='1'.
Just draw the diagram of these drivers with their enable signals, and see how you must control the enable signals to avoid contention (i.e. driving to strong values on a signal).
-- Paul.
Depends completely on what your model for port1 and port2 are doing. Do you have some form of VHDL model for the external 'things' that are driving port1 and port2? Are you trying to 'force' them? If forcing, how?
Since port1 and port2 are I/O pins on your design, then when things are just 'sitting there' (i.e. port1_output_enable and port2_output_enable are both '0') then port1 and port2 will be sitting there at 'Z'. When port1_output_enable goes to a '1', your design should start driving port1 (i.e. now it's an output) with whatever is on port2 (which is now an input). So, ask yourself, at that time, what is driving port2? The answer is that it is your simulation testbench, port2 needs to be driven, at that time, just like any other input to your design. Once you've got that understood, you'll need to answer the same questions about port1 when your signal 'port2_output_enable' is active.
KJ
Tanks for your answers ... Now it works - it was just a handling error of the Quartus Simulator by me (embarrassing) Manfred
"KJ" schrieb im Newsbeitrag news:O6cLg.15443$% snipped-for-privacy@newssvr29.news.prodigy.net...
Take a look at Analog Devices line of level translators -
Marc
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