Hi, I am designing a peripheral interface IO chip that implements a bidirectional bus with a microprocessor. The problem I have is that in one process, I have the bus as an input (that is forced during simulaton) and in another process, the bus acts as a output that routes the inputs to the microprocessor. When I use the bus as an output, the Modelsim simulation shows XXXXXXXX in the bus. Is this illegal to do? I have no idea of how to control the input/output configuration a bidirectional bus. Any help is highly appreciated. Here's my VHDL code
entity pioprocesses is port(
CE: in std_logic; RD: in std_logic; WR: in std_logic; A0: in std_logic; STB: in std_logic; RESET: in std_logic; IBF: out std_logic := '0'; INTR: out std_logic := '0'; MICROPROCESSOR_D_BUS: inout std_logic_vector (7 downto 0) bus := "ZZZZZZZZ"; INPUT: in std_logic_vector (7 downto 0) );
end pioprocesses;
architecture Behavioral of pioprocesses is shared variable writingcontrolbits: std_logic := '0'; shared variable qualifiedread: std_logic := '0'; shared variable readingstatusbits: std_logic := '0'; shared variable readinginputbus: std_logic := '0'; shared variable readingdataregister: std_logic := '0'; signal CONTROL_REG: std_logic_vector (1 downto 0) := "00"; signal DATA_REG: std_logic_vector (7 downto 0) := "00000000"; signal STATUS_REG: std_logic_vector (2 downto 0) := "000"; begin
mainprocess: process(CE, A0, WR, RD, STB) is begin writingcontrolbits := NOT(CE) AND A0 AND RD; readingstatusbits := NOT(CE) AND A0 AND WR; readinginputbus := NOT(CE) AND NOT(A0) AND WR AND NOT (CONTROL_REG(0)); readingdataregister := NOT(CE) AND NOT(A0) AND WR AND CONTROL_REG(0); end process;
writecontrolbits: process(WR) is begin if falling_edge(WR) then if(writingcontrolbits) then CONTROL_REG(0)