bi-phase decoding

Can anyone point me to some VHDL code for decoding bi-phase mark and space formats.

Thanks in advance...

Reply to
George
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I don't know of any code offhand, but the decoding is pretty durn simple. I believe the Mark and Space formats only differ in the polarity that is decoded.

Decoding requires a time base of some sort to time the period from the beginning of the cell and the middle. It does not have to be of a known period, but that certainly makes the design simpler.

The decoder circuit has to detect the mark (transition) at the boundary of each cell. If you just sample the input using your clock and watch for a difference between input and output, that will be the flag for a mark. Start by assuming this is the cell boundary. Hold the value of the current input and time a period which is approximately 3/4 of the cell period. Compare the input value to the stored value and that tells you if there was a mark mid-cell and give you your data value, 1 for a mark and 0 for a space. Then the circuit goes back to watching for the cell boundary mark.

Anytime there is a space, the mid-cell mark will be absent and if the circuit will naturally sync with the next cell boundary. I believe this decoder is just two FFs and a couple of gates, plus what ever it takes to generate your 3/4 cell period. Not a lot to it!

If your time base clock is not of a known period, you will have to measure the cell period and use that measurement to time your decoder. This design would be a bit more difficult since it has to align to a cell to measure it and you can't align to a cell without being able to time the mid-mark. Except that when you receive a space it will, again, naturally measure and align to the cell. Then all is good. So it will take a period of time to align to a cell, dependent on your data.

Reply to
rickman

It sounds to me like Manchester encoding. I published a 6-flip-flop design in the old XC3000 days, and we modified it 4 years ago to fit into one CLB (8 flip-flops) in Virtex. These designs assume that you know the bit rate by about plus/minus

25%, so it's pretty rugged, but not adaptive. If anybody needs it, send me an e-mail (You might also google with "Manchester Alfke" Peter Alfke, Xilinx
Reply to
Peter Alfke

Here is the original article. I googled "Manchester code" XCell:

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Peter Alfke

Reply to
Peter Alfke

Peter,

Manchester is close, but not quite the same animal. Manchester is bi- phase Level rather than bi-Phase Mark. Manchester gets its bit value from the direction of the mark and bi-Phase Mark gets its bit value from the presence or absence of a the mark.

For the OP, here is a good description of these encoding schemes, but I don't agree with the way they use the term "beginning of every bit period". Marks for both of these schemes are always present in the center of the cell and are data dependent for the cell boundaries.

Reply to
rickman

Opps, I mistyped. The marks at cell boundaries for Mark and Level encoding are mandatory. It is only Manchester or bi-phase Level where the mandatory transition is in the cell center.

Reply to
rickman

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