Hi
I have designed a little tristate bus matrix using Quartus 4.1 (web edition, SP1). The design uses tristate buffers and bi-directional pins that operate as both inputs and outputs (only one way at a time obviously). When I create a symbol for the design (call it symbol A) and use 'A' at the top level of my project, the simulation results are all as expected hence proving that my design works fine.
However, if I use 'A' in another .bdf file, add pins etc and then make a new symbol for this design, which in effect is exactly the same as 'A', and I call the new symbol 'B', if I use 'B' in the top level of the project and simulate it, the design doesn't work. This makes no sense to me at all as I am essentially using exactly the same design, but just at different hierarchical layers.
When synthesising the second way, I do get a warning about the preservation of boundary logic to do with bi-directional pins being used at different hierarchical layers. I have looked at the help files under "preserve hierarchical boundary logic option" and it recommends that I turn the "preserve_hierarchical_boundary" setting to off. I can't find this option in the Assignment editor as it suggests. Where would I be able to change this setting which supposedly would cure my bi-directional synthesis problem?
Has anyone else had this problem and if so, how did you overcome it? If somone could help me out it would be greatly appreciated!
Thanks Ryan