Bi Dir Synthesis Problem in Quartus?

Hi

I have designed a little tristate bus matrix using Quartus 4.1 (web edition, SP1). The design uses tristate buffers and bi-directional pins that operate as both inputs and outputs (only one way at a time obviously). When I create a symbol for the design (call it symbol A) and use 'A' at the top level of my project, the simulation results are all as expected hence proving that my design works fine.

However, if I use 'A' in another .bdf file, add pins etc and then make a new symbol for this design, which in effect is exactly the same as 'A', and I call the new symbol 'B', if I use 'B' in the top level of the project and simulate it, the design doesn't work. This makes no sense to me at all as I am essentially using exactly the same design, but just at different hierarchical layers.

When synthesising the second way, I do get a warning about the preservation of boundary logic to do with bi-directional pins being used at different hierarchical layers. I have looked at the help files under "preserve hierarchical boundary logic option" and it recommends that I turn the "preserve_hierarchical_boundary" setting to off. I can't find this option in the Assignment editor as it suggests. Where would I be able to change this setting which supposedly would cure my bi-directional synthesis problem?

Has anyone else had this problem and if so, how did you overcome it? If somone could help me out it would be greatly appreciated!

Thanks Ryan

Reply to
Ryan
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. I have looked at the help files

Hi Ryan, You can make this seting from the Assignment Editor->Logic Options Panel. Open the Assignment Editor and click on the Logic Options button in the upper right hand corner. Once this is done, if you click on the Assignment Name field you should see this setting in the drop down. This Assignment should be applied to the Instance of A for which you want to turn this value OFF. This is specified in the To field of the Assignment Editor.

Therefore the easiest sequence of steps is:

  1. Open the Project Navigator->Hierarchy Tab.
2.Find the instance of A for which hierarchy should not be preserved. 3.Right click on the instance and select Locate in Assignment Editor. You will see a row with the Instance name in there. 4.Click on the Logic Options button in the upper right hand corner of the Assignment Editor.
  1. Select the Preserve Hierarchy Boundary setting in the cell that is at the intersection of Assignment Name and the row in Step 3.
  2. Set the value in the cell adjacent to the cell in Step 5 under the Value column.

Hope this helps. Subroto Datta Altera Corp.

Reply to
Subroto Datta

Hi Subroto

Thanks for your response. This may be a really stupid question but I dont seem to have a 'logic options' button in the assignment editor! How do I display it?? I cant find where to turn it on in the 'view' options.

Thanks again Ryan

Reply to
Ryan

You need to use Quartus II 3.0 or higher. Look carefully in the upper right corner of the Assignment Editor. It is locate to the right of the Timing button and above the Check All button. On a side note the default value of the Preserve Hierarchical Boundary setting is Off. So if you did not turn it on in the first place, you are running into something else. One thing you may want to do is export the OE signal and the dataout as outputs from the lower level block and then feed them into a tristate upper at the top level.

- Subroto Datta Altera Corp.

Reply to
Subroto Datta

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