Typically FPGA BGAs have a central square of balls which are all connected to ground. What is the current wisdom on how to hookup the PCB tracking for the central ground matrix.
The simplest, and lowest inductance, seems to be to put down a solid square of copper covering the central ground ball pads, and pepper the square with ground vias. But that looks like the dreaded 'Solder Mask Defined' pads. Is it better to go with individual NSMD pads, tracking, and vias?
Possibly both missing the point. Usually the central ground matrix is for thermal conduction to the ground plane. Check with your assembly service, but usually placing a solid plane under the BGA with solder mask defined openings will adversely affect soldering. We usually use etch at about the pad size going diagonally to one via per pad. No thermal relief where the via attaches to the ground plane(s).
Central ground balls in these packages do carry DC current, but were placed where they are for better thermal conduction to a central die. Generally many more signal return grounds appear in the outer sections of the same BGA's.
Also check with the chip manufacturer for possible application information. I've also seen BGA packages with a single heat slug on the bottom requiring a special pad and solder paste pattern (Broadcom Gig ethernet PHY). A BGA that has sufficient thermal conductivity to the top surface usually works best with a heatsink rather than using the circuit board for heat spreading (Xilinx flip-chip metal top packs).
an excellent post! We use a criss-cross pattern of smaller traces going between the pads and vias, four narrower traces per gnd pad and per via. Makes it look nicer around the edges of the central cluster, but works much the same as yours! Cheers, Syms.
This all suggests that I can have an outer ring of vias in the center of a device (next to every "outer" gnd ball) and a copper pour on the top layer connecting the rest of the gnd balls with a few vias. I can then easily put some bulk decoupling right in the center of the bga as it is no longer peppered with vias. If this is the case then you have my thanks for pointing this out.
By the way, you say no current flows on the inner balls but surely they carry their share of the DC current?
We leave out an occasional via to squeeze in 0805 caps in this centre region. Works well on our FG676 parts with, IIRC, a 6x6 centre. The 0805s are 2mm long so they fit nicely into the via matrix. The 0805 pads are directly aligned with the FPGA GND pads, so the via fit into the gaps. HTH, Syms.
You are making a classic mistake: not much DC current flows either.
The static magnetic field will force the static electric field to be confined to the area adjacent to the current flow in the opposite direction.
This is not skin effect (where current flows on the surface at high frequencies), but a very simple EM rule, that is completely ignored!
Use of any 2&1/2 D or 3D (Ansoft) modeling tool shows this.
The most famous (and true) story of this was with the SF Bay Area Rapid Transit System (BART), in ~1974 or was it 1975?:
The design had a third rail, on the left of the train (from front of train point of view) carrying 1000V DC for the train.
The return was the two rails.
Obviously(?) the Westinghouse engineers reasoned that the return current would be equally divided among the two rails. 1/2 on right rail, 1/2 on left rail.
They designed a "train in block" detector to show where they had trains that detected when the two currents were balanced.
Day 1, they turn it on, and everywhere there is NO train, the light is ON (giant status board in Richmond, Ca). Everywhere there !is! a train, the light is OFF!
Westinghouse, Xerox (who did the computers?), and a host of consultants descend on UC Berkeley to ask the E&M Professors "what the h***?"
As they (professors) laughed and laughed, they asked the grad and senior students to figure it out with (for) the commercial engineers.
So, we all sat down, sharpened our pencils, got out our sliderules and textbooks, solved it, and voila! 2/3 in the left rail (nearest to the supply) and 1/3 on the right rail (furthest).
I was there in '70 or '71: I remember that the line and stations were finished, but there was some technical problem that prevented the trains running.
This link is also confused. They talk about ferrous vs non ferrous, and skin effect, too. The basic effect has nothing to do with ferrous or skin effects.
the only way a simulator can see DC current resulting from a static magnetic field is a software bug or, worse, misconcepted basics behind the software. If physics would allow that we would have unlimited energy for free... just put a magnet next to a conductor and off you go... :-)
Perhaps you meant moving (mechanically) a static magnetic field relative to some conductors? This would of course do the job.
I know you do not belive me. And you haven't ever solved Maxwells equations for this case (or else you would see it).
I am not going to convince you, so I will not try, but it is a real effect, and it really happens.
I also admit that it is greatly misunderstood (after all, Westinghouse believed as you do, util they made a million dollar mistake by building it, and experiencing it first hand).
Austin, I also think it is some kind of misunderstanding, of course.
Perhaps (if you refer to the railroad story) the motion came from the train moving, or something else they just did not take into account initially, things like that do happen.
However, for the case of the BGA socket, this cannot apply. If there is no DC current through the central pads it can only be because of higher active resistance or, more likely, because there is little if any (leakage only, I guess) DC current to talk about. Come to think of it, it should be that last one.
BTW, my (1.27 mm pitched) BGA designs all have a via hole in the center of each pad, this is OK if you run small quantities. The most important drawback is the necessity to once fry the BGA chips belly up with some flux, before you use them on the board, lest some of the balls get detached (come coldly soldered from chip vendor) and flow through the board forming a bubble .... (I had this several times until I figured out how to deal with the problem). The most important advantage is obviously having access to all the BGA pads with the scope etc.
Take a magnet near the front of a Shadow mask CRT, and you can clearly see the effect a magnet has on moving (dc) electrons. DC current requires electrons to move, even if the ammeter does not.
The outer wall of 6 is + (6+6+3+4, the perimeter), and all the inner 5X5 (25 conductors) are -.
Then look at the distribution of current at DC.
I did find one article on furnaces, which showed the proximity effect on carbon electrodes, but it also made mention of frequency effects, and seemed unclear on what they saw. They clearly saw what I describe in the plots of current. But, they also attributed it to the 50 Hz AC field (which is pretty absurd....skin effect at 50 Hz is negligable!).
As I said, well misunderstood. Even after looking at the answer, they explained it wrongly.
High school physics is sufficient to know you can deflect the beam of electrons because of the two interacting magnetic fields, the one the electrons produce when moving with the one you apply with your magnet. The DC current value remains unchanged, I hope you are aware of that.
Austin, I do believe you know what you are talking about.
I just do not accept the explanation - physics, as we know it, says it must be different.
I am pretty sure you don't just assume there is little, if any DC current flowing through the central BGA pads, you know it is so. It just cannot be explained by any static magnetic field, that's all. My assumption is that there just is no DC current, it can be measured as DC once it has been summed up in the power/ground plane capacitance, decoupling capacitors etc. With CMOS chips, you actually have only leakage DC current, which is orders of magnitude lower than what I believe we are talking about. The rest is only AC.
Austin did not claim that the current changes, just that it takes a different path. I look at it this way: Everything else being equal, the dc current would take the path that puts the least energy into the magnetic field. In other words, it minimizes the rea of the current loop. But opposing that is the resistive drop if all current were to use the smallest loop. So the current finds the right balance. Nature is smart, and consistent. Peter Alfke
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