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best way to get 4xclk

Hi,

What is the recommended way to get 4xClk from Clk?

Xilinx recommends not to use cascaded DCMs for jitter & skew problems..

Then is there any recommended way to get this?

Regards, JK

Reply to
JK
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What part?

What input frequency?

--
Phil Hays(Xilinx, but posting for myself)
Reply to
Phil Hays

Input frequecy is 50MHz. And required O/p frequency is 200 MHz.

Regards, JK

Reply to
JK

part is Virtex 2 Pro.

Regards, JK

Reply to
JK

Use the frequency synthesis method: the Fx output gives you a multiplied and/or divided frequency. x4 is actually the default option, but you can also multiply by any integer up to 32 and simultaneously (!) divide by any integer up to

  1. So you can take 50 MHz, multiply it by 29 and simultneously divide it by 17, to give you 82.352941 MHz, just to pick some really weird numbers. But you just want to multiply by4, which happens to be the default for the Fx output. Peter Alfke
Reply to
Peter Alfke

Thank you all for the timely support!

Regards, JK

Reply to
JK

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