Hi,
I have been working on a project and get the coding done and tested using Behavioral Simulation. However, I download it into the FPGA(Spartan 3), it wouldn't work. So I went back and discovered that the Post-route Simulation are all wrong. I had not encountered this before. What could be the source of the problem? Or is there specific areas which I could look at?
BTW, I am using Xilinx ISE 9.2i.
Thank You Andy
Most probably you're not meeting timing. Does it help if you run the design at a slower speed? It might be easier to check the simulation for lower speed. Check the timing reports. Also make sure that your constraints are setup correctly (all clocks defined, clock relationships defined, false paths added, multi-cycle paths multiply checked).
I had actually set to clk to a a very slow one. From the timing reports, I had actually meet all constrains and my design only use a single clock.
Andy,
Check pad report as well.
/MH
Post-route simulations fail for only one reason...timing.
- Does your testbench model the FPGA inputs with the proper setup and hold times? 'Proper' meaning it models the real world system which is also failing.
- Any asynchronous clocking going on? i.e. The clock input of a flip flop is the output of some other combinatorial logic or a flip flop? A purely synchronous design wouldn't have this approach, since you say you're running at a 'slow' clock speed, I'm guessing that you're violating a hold time requirement (which will happen independent of clock speed). Violating a hold time requirement is darn near impossible in an FPGA with a synchronous design but very easy when you have gated clocks being generated internallly.
KJ
ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.