Beginner help with VHDL, Xilinx 9536XL, and ISE7.1

So I need some help getting started with programmable logic and VHDL.

In the past all I have done in the programmable logic area are 16V8 and

22V10 PALs.

I actually feel kind of stupid about the simple questions I am about to ask, since it isn't like I don't know a lot about electonics. I have a BSEE and in the past I've designed DSP boards and motor controllers that control hundreds of amps and make electric forklifts able to lift thousands of pounds. Pretty fun stuff actually.

But I am stumped by a few simple things with VHDL, Xilinx ISE 7.1, and the Xilinx XC9536XL experimenter board I am using.

I've gone through ALDEC's Evita VHDL tutoral end to end and I think I've learned the basics of the language.

So my project was to write a program to take a step and direction input and output the proper sequences to control a stepper motor. But the logic output sequences I got didn't make sense, so I decided to walk before I run and just programmed up a couple very simple programs. More on that later.

So what I've got is an XC9536XL board I bought on eBay. I connected a

4 position dip switch with 4 pull up resistors connected so that when you turn on a switch the input is grounded and read as a zero. Turn off the switch and the pullup pulls high and it's read as a one. I know this works because I can measure the correct logic signal right at the CPLD.

I also connected 4 LEDs. The 4 LEDs are each connected to Vcc through a current limiting resistor. The other end of each LED is connected to an output of the CPLD. So sending a logic zero to the output should sink current and turn on the LED. The LEDs work because I can unplug them from the socket header and connect each to ground and the LED lights as expected.

The first "simple" program I wrote was to read the switch inputs and output them to the LEDs, using the following VHDL code in Xilinx ISE

7.1:

---------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Test1 is Port (SWITCH_IN : in std_logic_vector(3 downto 0); LEDS_OUT : out std_logic_vector(3 downto 0)); end Test1;

architecture Behavioral of Test1 is begin LEDS_OUT

Reply to
cdsmith69
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What did you use to design the 16V8/22V10's ? Why not use ABEL, for the 9536 ?

-jg

Reply to
Jim Granville

This is typically how LEDs are connected to a CPLD. VCC should be +3.3 volts, since the XC9536XL is a 3.3 volt part (with 5-volt tolerant I/O's). So, in order to turn on an LED, the CPLD needs to ground the LED's lead. (BTW: the LED is -->|-- ) so: [+3.3]-----[R]--->|---- [CPLD pin, or ground.] LED

If you had inverted the switches, then you should have seen the expected behaviour:

LEDS_OUT

You should be able to assign a 0 to each LED pin, and that should cause each LED to lite. LEDS_OUT 3. Why doesn't my counter count? Hmm... I'm a bit puzzled by this, too. Try making an up counter. Modify your code to count up only, and to not check the switch. Also, the perferred way to act on a rising edge clock is if rising_edge( CLK_in ) then

Also:IEEE.STD_LOGIC_ARITH and IEEE.STD_LOGIC_UNSIGNED are non-standard libraries. You're better off using IEEE.NUMERIC_STD, instead.

Out of curiousity, where does CLK_in come from and what is its frequency? And do you know that your LEDS_OUT CPLD pins are actually connected to the LEDs and not something else? After you've synthesized the code, look at the FITTER report. At the end of the report, it shows list of chip pins and the name that has been assigned to each chip pin. If they are wrong, you will need a UCF (User Constraint File). The simplest way to do this is to find the UCF that came with you board, and then select PROJECT->ADD Source and supply the name of the UCF. If there is no UCF file, then you'll have to create one. The Process box should show USER CONTRAINTS. Click on the [+] to expand it and click on ASSIGN PACKAGE PINS. This will bring up another screen that shows a drawing of the chip, plus a list of signals. It's then an easy matter of assigning your signals to the chip so that the signal match up with how the chip is wired on the board.

"thanks for reading it" You're welcome. I had a lot of problems like this when I was just starting out, too. And who knows, perhaps the board you bought from eBay has problems.

HTH

-Dave Pollum

Reply to
Dave Pollum

This is typically how LEDs are connected to a CPLD. VCC should be +3.3 volts, since the XC9536XL is a 3.3 volt part (with 5-volt tolerant I/O's). So, in order to turn on an LED, the CPLD needs to ground the LED's lead. (BTW: the LED is -->|-- ) so: [+3.3]-----[R]--->|---- [CPLD pin, or ground.] LED

If you had inverted the switches, then you should have seen the expected behaviour:

LEDS_OUT

You should be able to assign a 0 to each LED pin, and that should cause each LED to lite. LEDS_OUT 3. Why doesn't my counter count? Hmm... I'm a bit puzzled by this, too. Try making an up counter. Modify your code to count up only, and to not check the switch. Also, the perferred way to act on a rising edge clock is if rising_edge( CLK_in ) then

Also:IEEE.STD_LOGIC_ARITH and IEEE.STD_LOGIC_UNSIGNED are non-standard libraries. You're better off using IEEE.NUMERIC_STD, instead.

Out of curiousity, where does CLK_in come from and what is its frequency? And do you know that your LEDS_OUT CPLD pins are actually connected to the LEDs and not something else? After you've synthesized the code, look at the FITTER report. At the end of the report, it shows list of chip pins and the name that has been assigned to each chip pin. If they are wrong, you will need a UCF (User Constraint File). The simplest way to do this is to find the UCF that came with you board, and then select PROJECT->ADD Source and supply the name of the UCF. If there is no UCF file, then you'll have to create one. The Process box should show USER CONTRAINTS. Click on the [+] to expand it and click on ASSIGN PACKAGE PINS. This will bring up another screen that shows a drawing of the chip, plus a list of signals. It's then an easy matter of assigning your signals to the chip so that the signal match up with how the chip is wired on the board.

"thanks for reading it" You're welcome. I had a lot of problems like this when I was just starting out, too. And who knows, perhaps the board you bought from eBay has problems.

HTH

-Dave Pollum

Reply to
Dave Pollum

Most commonly was ICT pals with their WinPlace software, but I did use some AMD pals and their ABEL software, way back in about 1995.

Neither of these programs will work for the 9536.

Reply to
cdsmith69

I've got to get a real newsreader set up insted of using google groups. :-)

Yup, this is now it is wired. I did that because I noticed that the

9536 can sink a lot more current than it can source.

Will do, tonight.

I'll switch to that and see if it makes a difference. I did it the other way because that is what they always did it in the ALDEC VHDL tutorial I learned from.

Those were thrown in there by the Xilinx software when I created a new project. Being new to VHDL, I don't really understand what comes from what libraries yet. :-)

It comes from my function generator. Square wave output set to 3.3V. Looks clean on my oscilloscope. I had the frequency low enough that I could watch the count sequence on the LEDS, like around 1Hz.

Because the expected LEDS do light when I flip switches with "LEDS_OUT And who knows, perhaps the

Yeah. The company I bought it from has been selling it for years, but I guess that doesn't mean it's guaranteed to work right. I was looking at it since my original post and I realized that it doesn't really have proper bypass capacitors on it. There's just one 100uF electrolytic cap near the CPLD. I suppose if that is causing power problems then I might see issues with things like counters, but not with simple things like running the switches right to the LEDS. I think I'm going to tack solder a few bypass caps to the bottom and see if that changes anything.

Thanks for the help. If I figure it all out I'll post here so everyone knows what was wrong.

Reply to
cdsmith69

My guess is that you haven't defined which pin on the outside of your CPLD is connected to which signal on the inside of your CPLD. You've ended up with random signals to random pins, defined by the fitting tool to whatever made it's life easiest. The mapping will change every time you modify and resysnthesise the code.

You need to add a .ucf file to your project with the signal->pin mappings in it. It's just a text file, the format should look something similar to the following:

# DSP bus interface NET "XA" LOC = "p128"; NET "XA" LOC = "p102"; NET "XA" LOC = "p89"; NET "XINT1" LOC = "p130"; NET "CSn" LOC = "p100"; NET "RDn" LOC = "p103";

The .ucf file is also where you add your timing constraints, you should at least have one for your clock (when you're using one). That section will look like:

# Timing constraints NET "CLOCK" TNM_NET = "CLOCK"; TIMESPEC "TS_CLOCK" = PERIOD "CLOCK" 8 ns HIGH 50 %; NET "CLOCK" USELOWSKEWLINES;

These constraints have been cut from an FPGA project .ucf file, but I'm pretty sure that the syntax is the same for CPLDs.

Hope this helps!

Cheers, James

Reply to
James Kennedy

You do realize Xilinx has ABEL flows for their CPLDs ? [ Scan for .ABL files, in their examples directories]

You'll find the learning curve much shorter, and ABEL is fine at the smaller end of the scale.

Reply to
Jim Granville

The solution is simple, but far from obvious. You need to download and apply the patch for ISE 7.1 or install the latest service pack (4). There is a bug that inverts all of the outputs of CPLDs (with no service pack and also maybe SP1).

Go to

formatting link
select downloads, log in (or create a new account), then select your ISE version and OS.

Xilinx has refused to post this information to their download page. I even talked to a factory FAE and he could not get them to post it. The only way you can find out about it is to search their site for key words that match the article.

Marc

Reply to
news.guardiani

I think what you need is a design flow/ISE tutor document, it's somewhere on Xilinx web. Some more suggestions: Try using simulator (Model sim or Xilinx Sim in 7.1) Read the fitter report to see the implemented equations Also try the ChipViewer to see internal signals After all of these verification steps are done and the board still won't work as expected, Check your configuration method (JTAG? ), verify if your *.jed file has been loaded correctly? Now, you may think of a hardware issue Cheers,

Reply to
ccon67

I hadn't thought to ask what service pack he had downloaded. Perhaps SP4 will fix all of his problems. On the other hand, if there are _no_ bypass caps on the board, I assume that could cause problems, too. I wonder who he bought the board from.

-Dave Pollum

Reply to
Dave Pollum

One has to wonder how this schoolboy error got past their supposedly 'rigourous regression testing' - oh, maybe that is only for FPGAs ?

You could also move to ISE 8.1 ?

-jg

Reply to
Jim Granville

Bingo. That fixed everything. After downloading the 7.1.04 update, which was something like 325 megabytes, nearly as big as the full download, everything is working fine. My counter counts right, the outputs aren't inverted, and I can even directly assign pins to a value and have it work.

I spent a long time a couple nights ago searching their whole knowledge base section and reading everything I could find on the 9500 family CPLDs and never found this information. I only found it after I went to the download page for the service pack, and found the link that said something like "read this before installing" and somewhere in there was a list of what the update fixed, and in there was a short sentence or two saying that it fixed an issue with CPLD outputs being inverted. It never did mention fixing the problem where I couldn't directly assign a pin to 1 or 0 and have it work. Either way it came out as a high.

Right now, there isn't much I can say in polite company about how this makes me feel. This bug has cost me several days time. If I had been working on a real project at work, instead of hobby tinkering at home, it would have cost the company a lot of money in engineering time.

I think it is rather irresponsible of them to not at least have a notice on the download page for 7.1 saying you NEED the update to

7.1.04 if you are using CPLDs. And what they really should have done is taken down the 7.1 update and replaced it with a 7.1.04 full download, and also have the 7.1.04 update available for those who already have 7.1 installed.

Many thanks to you Marc, and to everyone else who posted their ideas. Now I can get around to doing something useful and maybe fun with this CPLD.

Reply to
cdsmith69

I tried posting this before but it doesn't look like it showed up in the group. I guess I really should get a real newsreader set up instead of using google groups...

Bingo. That fixed everything. After downloading the 7.1.04 update, which was something like 325 megabytes, nearly as big as the full download, everything is working fine. My counter counts right, the outputs aren't inverted, and I can even directly assign pins to a value and have it work.

I spent a long time a couple nights ago searching their whole knowledge base section and reading everything I could find on the 9500 family CPLDs and never found this information. I only found it after I went to the download page for the service pack, and found the link that said something like "read this before installing" and somewhere in there was a list of what the update fixed, and in there was a short sentence or two saying that it fixed an issue with CPLD outputs being inverted. It never did mention fixing the problem where I couldn't directly assign a pin to 1 or 0 and have it work. Either way it came out as a high.

Right now, there isn't much I can say in polite company about how this makes me feel. This bug has cost me several days time. If I had been working on a real project at work, instead of hobby tinkering at home, it would have cost the company a lot of money in engineering time.

I think it is rather irresponsible of them to not at least have a notice on the download page for 7.1 saying you NEED the update to

7.1.04 if you are using CPLDs. And what they really should have done is taken down the 7.1 update and replaced it with a 7.1.04 full download, and also have the 7.1.04 update available for those who already have 7.1 installed.

Many thanks to you Marc, and to everyone else who posted their ideas.

Reply to
cdsmith69

I thought about that when I saw that the 7.1.04 update was something like 325 megabytes. I figured maybe a full download of 8.1 wouldn't be much bigger.

But then I figured I'd end up having to learn a whole new user interface, or there would be some other bugs that would cause problems.

Does 8.1 pretty much look like 7.1, so it wouldn't be too confusing to upgrade?

Reply to
cdsmith69

I thought about that when I saw that the 7.1.04 update was something like 325 megabytes. I figured maybe a full download of 8.1 wouldn't be much bigger.

But then I figured I'd end up having to learn a whole new user interface, or there would be some other bugs that would cause problems.

Does 8.1 pretty much look like 7.1, so it wouldn't be too confusing to upgrade?

Reply to
cdsmith69

I thought about that when I saw that the 7.1.04 update was something like 325 megabytes. I figured maybe a full download of 8.1 wouldn't be much bigger.

But then I figured I'd end up having to learn a whole new user interface, or there would be some other bugs that would cause problems.

Does 8.1 pretty much look like 7.1, so it wouldn't be too confusing to upgrade?

Reply to
cdsmith69

I did realize that at first, but then I promptly forgot. :-) Besides, I really wanted to learn VHDL for when I progress on to bigger and better things.

Reply to
cdsmith69

Well, I've been trying to post with google groups, but I see that even after several tries my recent messages aren't showing up. Who knows, maybe someday they will make it here from google's servers. If you see multiple replies from me that are similar, that is why. Now I've downloaded and installed a proper newsreader so I shouldn't have to mess with google groups anymore.

I thought about that when I saw that the update from 7.1 to

7.1.04 was something like 325 megabytes, and thought that maybe the full 8.1 download wouldn't be much more.

But then I figured that I'd probably find a whole new user interface that I'd have to learn, or there would be other new bugs in the software, and I would just update to 7.1.04 and get my CPLD working.

Does 8.1 look and work pretty much the same as 7.1?

Reply to
cdsmith69

Bingo. That fixed everything. After downloading the 7.1.04 update, which was something like 325 megabytes, nearly as big as the full download, everything is working fine. My counter counts right, the outputs aren't inverted, and I can even directly assign pins to a value and have it work.

I spent a long time a couple nights ago searching their whole knowledge base section and reading everything I could find on the 9500 family CPLDs and never found this information. I only found it after I went to the download page for the service pack, and found the link that said something like "read this before installing" and somewhere in there was a list of what the update fixed, and in there was a short sentence or two saying that it fixed an issue with CPLD outputs being inverted. It never did mention fixing the problem where I couldn't directly assign a pin to 1 or 0 and have it work. Either way it came out as a high. Now it works with 7.1.04.

Right now, there isn't much I can say in polite company about how this makes me feel. This bug has cost me several days time. If I had been working on a real project at work, instead of hobby tinkering at home, it would have cost the company a lot of money in engineering time.

I think it is rather irresponsible of them to not at least have a notice on the download page for 7.1 saying you NEED the update to 7.1.04 if you are using CPLDs. And what they really should have done is taken down the 7.1 update and replaced it with a

7.1.04 full download, and also have the 7.1.04 update available for those who already have 7.1 installed.

Many thanks to you Marc, and to everyone else who posted their ideas. Now I can get on with my original project, and maybe have some fun and learn something with CPLDs and FPGAs.

Reply to
cdsmith69

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