basic chipscope pro query

Hello,

I am new to chipscope pro.i read lot of documents but unable to get exact information.i worked with counter example which works fine

now i implement a design of ram using VHDL,where i first write some data on specific address and then read from that location.i have synthesized and then i created cdc format file.

here is my entity declaration

entity ram1 is port( clk:in std_logic; wr_addr:in std_logic_vector(2 downto 0); rd_addr:in std_logic_vector(2 downto0); we:in std_logic; oe:in std_logic; din:in std_logic_vector(7 downto 0); dout:out std_logic_vector(7 downto 0));

end ram1

i can give inputs in xilinx simulator and perform functional verification.now my question is by using chipscope inserter and analyzer how can i verify my design especially where can i give my inputs such as wr_addr,rd_addr,we,oe,din.

any suggessions will be greatly appreciated.

please help its very urgent

Thanks in Advance Irfan

Reply to
irfan.mohammed
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Irfan, What ChipScope stuff have you tried so far? Syms.

Reply to
Symon

Hello Symon,

Thank you for your reply,

i looked at ug029,user guide and some tutorial.i want to go through chipscope inserter and then analyze it.

how can i verify a simple program? where i want to give some inputs and look at the output or signal.

i have synthesized and opened core inserter through xilinx and then i took one trigger with width 24 and i connected the input and output signals(this is where i am getting problem)

for example in xilinx simulator

entity ram1 is port( clk:in std_logic; wr_addr:in std_logic_vector(2 downto 0); rd_addr:in std_logic_vector(2 downto0); we:in std_logic; oe:in std_logic; din:in std_logic_vector(7 downto 0); dout:out std_logic_vector(7 downto 0));

end ram1

first i make write operation

normally in xilinx simulator i give we =3D1 and wr_addr=3D101 and din

10101010

then after some delay of 10ns i make read operation

i give we=3D0 re=3D1 ,oe_addr=3D101 and i get the output dout=3D10101010

now when i want to test in chipscope how can i give din,we,wr_addr

and after 10 ns sec how can i give inputs we,re,oe_addr

Its very urgent or else u can give some example other than counter using core inserter and analyzer.

Thanks in advance Irfan

Reply to
irfan.mohammed

There may be a way to do that but I doubt it's in Chipscope.

You supply input signals din, we, wr_addr etc just as you normally do in your FPGA. That is, you cannot test a RAM on its own; it must be part of a system (e.g. including a Microblaze processor which writes and reads the RAM)

Chipscope will show you whatever activity is on these signals - like an oscilloscope or logic analyzer - but it is not a stimulus generator. (unless things have changed a LOT in 10.1!)

- Brian

Reply to
Brian Drummond

Hi Irfan,

You have several options for you problem. There are two Chipsope cores that you could use: ILA - integrated logic analyser VIO - virtual IO

The ILA is used to capture a consecutive set(or sets) of signals whenever the triggered. Similar to oscilloscope or real logic analyser. The VIO is used to send or monitor the current state of signals. You can also send some simple signal sequence, but I do not think you can capture consecutive signals iwth VIO.

For inserting the core you need to:

  1. generate the core
  2. insert the core: a) directly into the pre generated deisign netlist using the core inserter b) use the Chipscope core as a module in ISE flow.

ad a) Write down the nets you would like to monitor. Generate the Chipscope core with appropritate number of IO ports. The run the Core Inserter and connect the core to appropriate nets in your design netlist. Then run the ISE P&R. ad b) Simply use the CS core as a submodule in you design. After generating the cores you get some examples for module declaration and instantiation - use them. If you plan to alter the design use this approach, it will save you a lot of time, since you do not have to re- insert the core each time the netlist is altered. BTW: The Chipscope netlists (*.ngc) must be copied to your ISE project dir prior running P&R!!!

Cheers,

Guru

Reply to
Guru

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