Hello,
I am new to chipscope pro.i read lot of documents but unable to get exact information.i worked with counter example which works fine
now i implement a design of ram using VHDL,where i first write some data on specific address and then read from that location.i have synthesized and then i created cdc format file.
here is my entity declaration
entity ram1 is port( clk:in std_logic; wr_addr:in std_logic_vector(2 downto 0); rd_addr:in std_logic_vector(2 downto0); we:in std_logic; oe:in std_logic; din:in std_logic_vector(7 downto 0); dout:out std_logic_vector(7 downto 0));
end ram1
i can give inputs in xilinx simulator and perform functional verification.now my question is by using chipscope inserter and analyzer how can i verify my design especially where can i give my inputs such as wr_addr,rd_addr,we,oe,din.
any suggessions will be greatly appreciated.
please help its very urgent
Thanks in Advance Irfan