bare-metal ZYNQ

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Assume I'm a pointy-haired boss trying to help one of my guys.

I think that...

The Xilinx ZYNQ (FPGA+ARM on a chip) has a hard boot loader. It
figures out what the boot device is (serial flash, SD card, whatever)
and reads in a secondary boot program, which the Xilinx tools provide
as part of a build. That loader then reads the entire FPGA config
bitstream into DRAM, and sets up a giant DMA transfer to configure the
FPGA. That's all standard in the tools.

But what if there's no DRAM? My guy thinks he will have to write his
own ARM application, which is booted at load time, and inside that
would be a routine to read from the boot media and configure the FPGA
in chunks, using a small uP RAM buffer, maybe DMA or maybe not. He
figures he could do that in a few days.

Seems to me that Xilinx should support booting up a ZYNQ without DRAM.
Does the tool chain support that (people here think not) or is there
some loader already coded somewhere?

(Our support, through a distributor, isn't very good.)

Thanks





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John Larkin         Highland Technology, Inc
picosecond timing   precision measurement  

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Re: bare-metal ZYNQ
Am 13.06.19 um 01:32 schrieb John Larkin:
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A Zynq without RAM is like a car without tyres.

Maybe you can peek in the sources for the Red Pitaya; it is also
based on a Zynq and there are a number of Linuxes available
for it. I have one, but have avoided digging that deep.

If the loading interface is only remotely similar to other
Xilinx FPGAs, it should be easy to replace the one large DMA
xfer by many small ones.

regards, Gerhard



Re: bare-metal ZYNQ
wrote:

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There's enough of sram internal to the chip for many applications.

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Yes, but I was thinking that someone has already done the work.


--  

John Larkin         Highland Technology, Inc
picosecond timing   precision measurement  

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Re: bare-metal ZYNQ
On a sunny day (Wed, 12 Jun 2019 16:32:35 -0700) it happened John Larkin

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That thing runs Linux?
Does not Linux use the DRAM?


If not using Linux and DRAM then a simpler cheaper FPGA board?


Re: bare-metal ZYNQ
On Thu, 13 Jun 2019 06:14:09 GMT, Jan Panteltje

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I said "bare metal."

Separate FPGA and CPU chips is an option that we use a lot already,
but it needs a chip-chip parallel interface that uses a lot of balls,
or a slow SPI link.

The NXP uP that we usually use for this combo, LPC3250, looks to be
EOL, so we're looking for a next-generation product platform.  


--  

John Larkin         Highland Technology, Inc

lunatic fringe electronics  


Re: bare-metal ZYNQ
On 13/06/2019 17:09, John Larkin wrote:
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Consider NXP's i.mx RT family.  They have Cortex-M7 cpus at about 600
MHz, and have quad SPI or octal SPI links.  These are typically for
flash for booting, but you could use one link for the flash and one for
a high speed interface to the FPGA.


Re: bare-metal ZYNQ
On 13/06/2019 16:09, John Larkin wrote:
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May not be relevant right now but you could look at the ST M-7s as a  
step beyond the NXP part.
STM32H7...  400Mhz, lots of RAM and flash on chip 64 bit FPU, and multi  
bit SPI ("dual quad SPI" in ST speak) which would ease that uP<->FPGA  
bottleneck a bit. They claim max 133 MHz clock on it so with 8 bit data  
that's quite quick. The downside is that the FPGA will need to pretend  
it's a flash memory but that may not be too hard.

MK




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Re: bare-metal ZYNQ
On a sunny day (Thu, 13 Jun 2019 08:09:16 -0700) it happened John Larkin

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OK, just did a read of the 80 pages datasheet of the LPC3250.
While reading I was thinking about the chip in the Raspberry pi
 Broadcom BCM2835 -- 2837
but that has no ADC.. but does have HDMI out..
There exists a FPGA plugin board for the Raspberry.

It is a pity that so many things go EOL in a short time,
OTOH it is a throw away society.
And very strong competition does kill some products.

It all depends on what you want to do.

A Raspberry plus some external ADC 35$ + ??
VERY powerful platform, really, GCC compiler, Linux, lots of I/O.
USB, Ethernet, HDMI, analog video out, analog audio out,  
GPIO for extra boards... SDcard, camera interface, logic level serial, PWM,
PLL frequency generators, and although every year a new model, the  
basics stay more or less the same, quadcore now, lots of DRAM,
availability...

Depends on what you call 'bare metal' these days.
 https://en.wikipedia.org/wiki/Raspberry_Pi

I have several in use...

It is sort of moving to an ever higher level of integration.

Re: bare-metal ZYNQ
On 13/06/2019 18:35, Jan Panteltje wrote:
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Jan - do you know of a good, simple and fast way to get the Pi to  
exchange data with an adjacent chip (uP or FPGA). Using USB or Ethernet  
doesn't count as simple (or very fast for small data packets.)

MK

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Re: bare-metal ZYNQ
On a sunny day (Fri, 14 Jun 2019 09:11:36 +0100) it happened Michael Kellett

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Sure, first for FPGA there is this:
 http://www.latticesemi.com/en/Products/DevelopmentBoardsAndKits/RaspberryPiFPGA
this connects via GPIO.

I notice a lot more big names have now FPGA stuff for raspberry..
 Just google 'raspberry FPGA board;.


Depending on your definition of 'fast' with a micro,
the Pi had logic level RS232 via /dev/ttyAMA0,
also hardware SPI (or software SPI of course), i2c the same.

Here used as a a large LED matrix display driver:
 http://panteltje.com/panteltje/raspberry_pi_FDS132_matrix_display_driver/index.html


You can also use 8 bits from GPIO and do byte level transfers,
a typical example of 'fast' is this:
 http://panteltje.com/panteltje/raspberry_pi_dvb-s_transmitter/
that also uses a FIFO hardware buffer to get a smooth timed data stream
even during OS task switching.

8 bits (or more) transfer with handshake will work with most micros.

Here the Pi as JTAG programmer:
 http://panteltje.com/panteltje/raspberry_pi/

Stepper motor driver, lots of other i2c chips..
 http://panteltje.com/panteltje/xgpspc/index.html


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USB is slow on my older Raspberries at least, ethernet is OK.
I would prefer ethernet in some applications because of the galvanic isolation.

What is simple?
Everything is simple once you have dunnit.


Re: bare-metal ZYNQ
On 14/06/2019 10:44, Jan Panteltje wrote:
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Thanks for the stuff Jan, I don't think I explained quite what I meant  
by fast (although I did say that Ethernet wasn't fast enough).

So fast for me, for the applications I have in mind is:

round trip < 1us (less than 50ns preferred) - easy to do with FPGA  
memory mapped to uP and pretending to be a RAM - but I don't see how to  
do it on a Pi.
Sustained data transfer rate > 100MiB per second in both directions  
simultaneously.

You can do this kind of stuff with the Prus on the Beagleboards but it  
would be nice if it were possible on a Pi.

Simple means (in this context) not using lots of other fancy chips over  
and above the FPGA and not needing to use a GHz serial interface.  
(although if the PI had one spare that I don't know about I might have a  
go.)

I had wondered if the the camera or audio interfaces might be re-purposed.

MK



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Re: bare-metal ZYNQ
On a sunny day (Sat, 15 Jun 2019 13:14:27 +0100) it happened Michael Kellett

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Audio I do not think is usable for that, but who knows...
AFAIK the camera interface is from camera to board, so one way.
What I meant is if you have 8 or more GPIO pins, say a byte
then there is nothing stopping you from putting a byte on that,
and use a pin as handshake 'new data'.
FPGA would read the handshake and read the byte, and then set a ready pin,
Pi would then output he next byte,  
Now you have 10 pins and maximum I/O speed.
Same for 16 bits 18 pins.
The throughput problems is set by the Pi Linux multitasker, it will
interrupt the stream every now and then for a few milliseconds at least,
That is where you need the FIFO.
But that FIFO can be in FPGA RAM, no external logic needed as I do here:
  http://panteltje.com/panteltje/raspberry_pi_dvb-s_transmitter/
I did consider doing that in FPGA, but that seemed a bit of overkill in this case.

So then maximum speed boils down to hwo fast the Pi can output data really..
have not tested that, as I never was close to that limit.
It is simple to test, write some I/O pin toggle routine in asm, or even C,
and look at the scope.
loop:
out 0x00
out 0xff
goto loop  

Pi has DMA, have not used it myself, here some discussion:
 https://www.raspberrypi.org/forums/viewtopic.php?t83%76

Maybe this is of more use to you:
 https://github.com/hzeller/rpi-gpio-dma-demo

They did the pin toggle and:
<quote>
 The resulting output wave on the Raspberry Pi 1 of 22.7Mhz, the Raspberry Pi 2 reaches 41.7Mhz and the Raspberry Pi 3 65.8 Mhz.
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Fast enough?


Re: bare-metal ZYNQ
On 15/06/19 13:14, Michael Kellett wrote:
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You could do that on the XMOS xCORE devices. They are
fast enough to take the 100Mb/s serial ethernet traffic,
and process it in software. *And* be doing other things
at the same time, guaranteed by design (not tests!) :)

The IDE states the maximum timing between two points,
e.g. two i/o operations, or loop times. That's possible
since there are no caches, no interrupts, and the
latency is <100ns (much less in my experience).



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The xCORE i/o is very nice, easy to use, and is
similar to FPGAs in flexibility (e.g. SERDES,
or strobes, or...)


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Re: bare-metal ZYNQ
On 2019-06-15 14:14, Michael Kellett wrote:

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100 MiB as in 100 Mi Bytes (rather than bits) per second, full duplex?

That does not look realistic without some high speed serial interface.

As the rPi does not provide any, maybe other similar boards:

- ROCKPro64 (with Rockchip RK3399 SoC) has a PCIe x4 port
- Banana Pi M2 (with Allwinner R40 SoC) has a SATA port

PCIe x4 should easily do it, even when not using all those 4 lanes.

SATA might be somewhat tricky from the controller side, but it can work
if the FPGA target can emulate a block device.

Depending on controller capabilities, this could mean mostly half-duplex
transfers however. That would require SATA 2 with 3 Gb/s minimum (SATA 1
with 1.5Gb/s would be enough if the bulk transfers are full duplex).

Re: bare-metal ZYNQ
On 2019-06-13 17:09, John Larkin wrote:
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The chip-chip parallel interface is quickly becoming a chip-chip serial
interface, now that most higher-end embedded CPUs have PCIe.

NXP i.MX series has many variants with PCIe. So do many DSPs from TI.

It looks like nowadays PCIe gets to be the go-to interface both between
CPU and DSP and between CPU (or DSP) and FPGA. Few balls and high speed.

For CPU-DSP, the application CPU is the typically the root complex and
the DSP(s) is(are) typically the endpoint(s). The endpoint side can send
interrupt packets when it has data (or otherwise requires attention).

Regards
Dimitrij

Re: bare-metal ZYNQ
On Wed, 12 Jun 2019 16:32:35 -0700, John Larkin wrote:

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Our Zynq 7 boards have DRAM (natch) but we choose to load the PL (FPGA  
fabric) after boot rather than as part of the FSBL.

What you want to do is possible, but you won't get much support from  
Xilinx.  You will also lose some of the built-in security features.
Considering the costs of DRAM (plus the extra PCB layers you will need)  
you might be better off putting it on the board.  I'm assuming you don't  
have really large volumes, of course.

Allan

Re: bare-metal ZYNQ
On Wednesday, June 12, 2019 at 7:34:09 PM UTC-4, John Larkin wrote:
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You're in the Bay Area, right?  I've had good experiences with the Avnet Xilinx FAEs out there.  I can put you in touch with some folks if you need.

There is a reference design for running out of On-Chip Memory (OCM):
https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842377/Zynq-7000+AP+SoC+Boot+-+Booting+and+Running+Without+External+Memory+Tech+Tip

It's worth reviewing UG585 - Zynq-7000 SoC TRM, Chapter 6: Boot and Configuration as well.  Section 6.4 - Device Boot and PL Configuration is particularly helpful here.
https://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf

In a lot of cases, the PL is configured by the FSBL, which can be run from OCM and it's rather trivial to enable that in the Xilinx SDK.  

Re: bare-metal ZYNQ
On 6/12/19 7:32 PM, John Larkin wrote:
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It has been awhile since I used that chip, but my memory was that what
you are describing was the two stage boot loading process. There is a
First Level Boot Loader put into the internal flash of the device that
loads a program into the internal SRAM of the part from a limited
selection of sources (mostly limited to what you could load from with a
simple boot loader). This program is often just a Second Level
Bootloader, but could also be a simple 'bare metal' program. The Second
Level Bootloader generally had the ability to configure DRAM and load
the program it was loading into it, but it did not need to.

The other task normally done by the Boot Loader was to load the
configuration data into the FPGA, but that could also be put off till later.

When Booting to Linux, the Second Level Boot Loader actually just loaded
GRUB, and then GRUB loaded Linux and started it. GRUB and Linux required
DRAM, and much of the documentation assumes going to Linux, but the
tools did support other configurations.

Re: bare-metal ZYNQ
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Hmm... it's not the same, but on the Intel Cyclone V parts (and others I
think) there's just a FIFO.  You can push in bitstream words, and
configuration only happens when the full bitstream is provided and it meets
some kinds of checks.

The Zynq appears to drive such a process via DMA - the PCAP in chapter 6 here
https://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf
It doesn't say as much, but I wonder if it's possible to transfer in chunked
DMA.  The Linux driver probably has to chunk anyway, given the RAM buffer
you want to transfer may not be in contiguous physical memory.

As to support for this in the tools, without DRAM you're probably running a
custom OS, so there's a limit to what they can do.

On the Arria 10 one 'normal' boot process is: ROM bootloader reads SD card,
starts u-boot, which writes FPGA bitstream then boots Linux.  Now you
mention it, I think u-boot must be running without DRAM because the DRAM
pins are only configured by the bitstream.  So it could be worth looking to
see if a similar process works on Zynq.

(instead of SD card, QSPI and other storage is also selectable)

Theo

Re: bare-metal ZYNQ
As others mentioned: there is 256kByte OCM on Zynq.
I assume you want configure the device from flash.

Step 1: FSBL
Step 2: start u-boot (with fpga configuration support)
Step 3: configure u-boot to configure the fpga
Step 4: let u-boot load and start your bare metal application

Bart Fox

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