Hi,
why is nstate bad syncronous? It works when I remove rising_edge(clk_250k)... (I want to generate a signal which is a clock at 250k but with period of the clk_8m)
nextstate:process (clk_8m,clk_250k) begin
case state is when state1 =>
if clk_250k='1' and rising_edge(clk_250k) then state if clk_8m='1' then nstate if clk_8m='0' then nstate
Hi,
this works now in the simulator and is synthesizable. But is it a good methodology too? Actually I would like to add a if clk_8m'event to the top of the process, but this is not synthesizable.
nextstate:process (clk_8m) begin
case state is when state1 =>
if clk_250k='1'then state if clk_8m='0' then state
Hi,
I have tested it now on the board and it doesnt work? Does anybody know why?
regards, Benjamin
-- Mike Treseler
Hi,
this works now... Does anybody have a better way to do it?
nextstate:process (clk_8m) begin if falling_edge(clk_8m) and clk_8m='0' then case state is when state1 =>
if clk_250k='1'then state lcd_tick
This and other issues !
- Spend more time verifying and studying existing good code.
- Don't use a 250 kHz clock.
- Don't write processes like the ones you posted.
- Understand what clock domains are and what issues they bring.
- >>> And SIMULATE !
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