I am trying to synthesize this piece of code entity Coin is Port ( reset : in std_logic; quarter : in std_logic; dime : in std_logic; nickel : in std_logic; isselvalid : in std_logic; d2 : out std_logic_vector(3 downto 0); d3 : out std_logic_vector(3 downto 0); coinval : out integer range 0 to 95); end Coin;
architecture Behavioral of Coin is signal temp : integer range 0 to 95; begin
process(reset,quarter,dime,nickel,isselvalid) begin if reset = '1' then d2