Back to max thermal and power for XC4VLX200's

John,

The per ball current limit is more than 250 mA.

There are thousands of bumps per die to the package, so no problem there.

The package power and ground planes are solid copper sheets.

If you have ~160 Vccint pins (for a ff1760 package).

That is > 40 amperes. At 1.2 volts, ~ 50 watts.

I just don't think the package, resistance, bumps, balls, silicon, is going to be the weak link.

The weak link here is the design engineer.

Did they provide a good enough power distribution system?

Did they engineer enough cooling?

Our FPGAs will do a lot: you need to know how best to use them if you want to squeeze this kind of power out of them. I think it would require a liquid cooling solution.

Austin

My PCB's yes ... the question is just what is the construction and limits of Xilinx's package pcb that acts as the carrier for the die.

Do we? There have been some pretty strong statements here it's only a thermal limit.

So you test it with 10 lots of chips that all happen to have process variences to support a higher current profile. Then start building with a lot of chips that are at the other extreme ... say etching took the traces 20% under at spots due to photomasking failures ... but well inside the PCB mfg's stated tollerances for the build quote. I've always been uncomfortable with doing designs that way. Trail and error is not s substitute for engineering.

I'm not sure that's the case, but there are nagging questions pointing that way with some experience, the current lack of hard data and trying to make conservative design assessments.

It may simply come down to their using the old rules of thumb that only

15-25% of the design will be active, and scaling needed resources to that number. When I was doing the XC4VLX200 design last year the local FAE was dead sure that I only needed to use power estimator numbers in that range. A number of demonstration programs hit older XCV2000e's and XC2V6000's a lot harder ... like packing them with RC5 cracking engines, or distributed arithmetic engines. I was off by a factor or 3-5 on power estimates.

RC may tend to push the active design portion of the chip to numbers near 100%, and with it much higher toggle rates than a typical hardware controller design.

My cooling solution has been water or phase change on high density designs for a couple years, with heat exchangers directly attached/integral to 1/4" or 3/8" milled copper plate heat sinks spaning 16 to 64 parts per board. Air just can not carry enough heat away in dense designs.

Thanks for the specific data on the per pad currents. Did I misscount the VccInt pads? I only get 140 on the 1513 package listed as the only option for the LX200. That would lower the dynamic power limit from 50W to about 44W by your numbers.

actually a bit lower than 44W if the worst case design current is fixed at 250ma/pad during clock current peaks, and the average current is lower.

Peaks are ~ 10X average, with no issue in current handling.

With that much stuff switching, I doubt seriously you would see any real narrow peaks.

The clock is spread out over 2 ns of distance/speed of light on chip, and the switching is as well.

You can not get the whole core to "switch at once."

It just is not physically possible.

Now, since you have just learned (from Xilinx) how we do all the deep sub micron engineering so you do not have to, I will submit my bill and we can move on to more interesting topics?

Austin

I thought these top end FPGA's, were flip-chip, no bondwires stuff ?

-jg

Interesting - plausible, if they were 'several'. The type of ring Osc I expected was not "many of the fastest", but one, designed to be longer and slower - you are trying to get a physical verify of the silicon/process/temp/vcc ability, and you want to avoid local heating.

-jg

Yeah ... for LX200's certainly true.

With just the Tckskew for the LX200 being 1.2ns, 500Mhz/2ns would yield a fairly smooth distribution. Small parts don't have that problem, and would tend to cluster around clocks more, as the skew is about the same as a LUT delay. But likewise, because of the skew, a large RC design with a single clock would be forced down below 200Mhz on an LX200, and the clustering is likely to reappear in the first 1.5ns of the clock period.

Hmm ... I missed that full lesson ... shucks :(

Anyway yes ... you have been far more helpful than others I've asked. And while it's not at the detail I would like, I can live with the general validations for today.

They are. but instead of mounting the chip on the pad side of the pcb carrier, they are solder bump (AKA very small balls) mounted to the other side of the pcb carrier and use vias to get to the BGA pads on the other side. The bump pitch is much tighter than the BGA pitch, and it allows them to have more pwr/gnd bumps/pads than are on the other side for the pcb BGA. And as Austin pointed out, it allows them to use a multilayer pcb carrier to have pwr/ground planes in the carrier pcb to spread out the current more evenly, and probably act better as a bonding side heat sink.

This also means that the "trick" of issolating a VccInt and Ground pair doesn't actually measure the die voltage, but the pwr/gnd plane of the carrier, and there will still be a voltage drop from the via, traces and pads to the bumps.

No, but you can measure the GND voltage on the die that way. That's half the answer you want.

Allan.

No. But one can measure the carrier ground plane, which is half way to half of what I want :)

You can measure the GND on an IO ring, and that can still be usefull - that is the method used to test for crosstalk.

Measuring via a sense-routed bump, will likely get you much more than 'half way' to the Core Vcc - because there are very many, very short bumps from the carrier plane, to the die, and the PCB traces/vias that go back to the regulator are included in the other leg. The powersupply controller can also do what it likes with the Sense Feedback, and Current information, so you can, (if it really matters to you), regulate a virtual point ahead of the sense point, to a stable voltage. - jg

Howdy Austin,

Could you provide a bit more detail on this? UG112 seems to say that theta JB varies too much from situation to situation to be worth publishing. If it has even more impact on cooling the device than the theta JC, it seems like more information should be provided.

Furthermore, how much closer to 0 degC/W could the thermal resistance be, compared to the ~0.6 degC/W of the flip-chip packages? Or were you referring to everything except flip-chip?

Isn't the heat spreader on the flip-chips also copper? It seems like going through one tiny layer of thermal grease and one layer of heatspreader would have less thermal resistance than bumps + epoxy + substrate + ball + pad + via + ground plane. I don't see mention that the substrate has a substantal amount of copper in it, but that doesn't mean it isn't there and just not well documented.

I think you are referring to non-flip-chip here?

Thank you!

Marc

Marc,

I was only talking about flip chip.

The die vias, metal, bumps, planes, vias and balls are all metal. They conduct heat very well. They are very shot lengths. The epoxy and pcb material also is a great conductor of heat.

The grease and copper top is good, but not as good. Especially after

800 microns of glass (the backside of the die). Further to go. And then one more interface to the air (teriible) or to a heatsink (also may not be very good).

For all the details, you would have to contact your FAE and have them discuss a particular case with our packaging department.

Aust> Aust>

Austin,

I understand now. Thanks for the response - among other things, the glass on the backside of the die was something I overlooked.

Thank you,

Marc