Hi:
I spent the last two weeks at Xilinx in San Jose taking Doulos' "Comprehensive Verilog" and the "Essentials and Design for Performance" courses.
Very enlightening.
I was very impressed by the facility. Makes my workplace look a bit dumpy :-(
But I do have lots of oscilloscopes and cool toys :-)
Particularly cool were the badges and doors. Just stick the badge near the reader and you can get in where you belong. At my work (surprising as it is for a gov. lab) we have 4 generations of incompatible locks with no centrally networked control, with key pads, swipes where you have to stick in your badge from underneath, and they are half broken all the time.
Yes I know it's kind of silly to be focusing on the door locks after such an experience.
I am highly obsessed to start designing new circuits with my FPGAs now! I'm also overjoyed that the Linux tool-chain works so well. I can even program my Digilent boards in 5 seconds at the CLI rather than spending many minutes wading through Impact dialogs.
The instructor was very competent and fun to interact with. The people in the classes were very nice and professional. Just as I was hoping, a great deal of concepts relating to how to use Verilog and the tools to design properly--concepts that are difficult to get from language ref. books, and cookbook example books--were solidly conveyed through this training. A great experience! I feel now that, while I don't know deeply how to do everything, I know about it all in such a way that I can build up my experience much more efficiently now on my own. Most importantly, I think many blind spots have been eliminated.
The instructor tried to persuade me to consider switching my current design to Kintex-7 or Artix-7 vs. the Spartan 3E that I was targeting.
Now that I see Spartan 3 series are at the bottom of the Xilinx product offerings list, I have at least decided that I will consider moving to Spartan 6. So I bought some new dev. boards for Spartan 6.
But 7 series devices are either 30 times more expensive or unobtanium. Considering that I usually use single digit percentages of the resources of my PLDs, I think I'll be fine with Spartan 6.
I hope that some of the folks who took the courses will find their way to this group and begin to participate. I let them know about comp.arch.fpga.