We have two of these boards (with the LX50 ES), and both failed the DDR memory test with a build from the Base System Builder. We downloaded the test designs from the Avnet Design Resource Center, and these would sporadically fail.
We looked at the datasheet for the MT47H16M16BG DDR2, and noticed that the acceptable frequency range for the DDR is between 125MHz and
200MHz. The BSB design uses 125MHz, and according to our FAE, the test design uses 200MHz. Apparently our boards are marginal at both these extremes. We modified the clock generator in the BSB design to set the clock to 133MHz and 150MHz, both of these designs passed the memory test.As an aside, when I recompiled my EDK libraries for 9.2, I told it not to recompile any deprecated cores. Now it looks like there are only PLB cores availible, is Xilinx phasing out support for OPB?
We are using EDK/ISE 9.2 with the latest web updates.