Hello everybody!
I am slowly making my way getting our custom Xilinx Virtex-4 based board to work. Today I got as far as running the Base System Builder (BSB) from the Embedded Development Kit, selecting our own board and getting a memory test by just clicking "Next" a few times and "Finish" at the end.
What I would like to do is to have BSB add some tweaks required for the early silicon Virtex-4 on the development board in order to work around the issue described at
What I managed to do is to create a custom peripheral based on a netlist from Xilinx that implements this for any given MGT pair. The peripheral also allows to select the MGTs to connect graphically. As I know that I will forget to add these peripherals sooner or later, I'd like to automate adding them.
What I tried is to add an IO_ADAPTER section to the XBD file but for some reason it is ignored by BSB. The only port that is connected to the work around component is a clock line. Interestingly, when I connect the clock from the system reset input as in
BEGIN IO_ADAPTER ATTRIBUTE CORENAME = rio_workaround ATTRIBUTE INSTANCE = rio_workaround_0 PORT GREFCLK_IN = sys_rst_n # works!? # PORT GREFCLK_IN = ext_osc_clock !!! does not work, peripheral not created PARAMETER C_MGT_LOC_A = GT11_X0Y2, IO_IS = C_MGT_LOC_A PARAMETER C_MGT_LOC_B = GT11_X0Y3, IO_IS = C_MGT_LOC_B END
in the board definition file, it "works" - kind of, as the work around needs a real clock. Using ext_osc_clock instead, the peripheral is not even instantiated.
What I really want is the output of the DCM module that BSB creates automatically, but I have no idea how to access it in the XBD file. The clock source is defined like this:
BEGIN IO_INTERFACE ATTRIBUTE IOTYPE = XIL_CLOCK_V1 ATTRIBUTE INSTANCE = clk_100 PARAMETER CLK_FREQ =100000000, IO_IS=clk_freq # 100 Mhz PORT SYS_CLK = ext_osc_clock, IO_IS=ext_clk END
Any hints from some Xilinx expert?
Greetings, Torsten