Target FPGA: Virtex II PRO I generated 2 designs including 4 AURORA single lane CORE each, configured in streaming : The first 4 are on bottom edge in the first design and the others are on TOP edge in the second design.
While testing transmission with external hardware loopback, I got some lanes working well and others not. On the "bad" lanes, I detect received valid data while transmit is not activated. Depending on the lane, the received unexpected values are not the same and not at the same pace ( I implemented an error counter).
With loopback "internal parallel mode" , I have no more errors but with "internal serial mode" I notice the same behaviour as with my external loopback.
Could you help?
Thanks in advance