As I have a problem in asynchronous FIFO design. My case is described as below,
I want to design a FIFO as write in clock VD domain, and read in clock CP domain. And there is a signal (VD domain) informs 32-bytes is completed write to FIFO, then can be read out in clock CP domain, and guarantee there is not any data coming in the read out phase.
The RTL code is below, It's passed in simulation phase. My problem is can it pass the synthesis phase? Will it have any issue? Thanks.
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// // assume clk_cp = 50 Mhz, clk_vd = 30 Mhz. // input data and enable input datain_en; // based on clk_vd, high active input [7:0] datain; // based on clk_vd;
// assuming write 32 bytes data, will send a completed packet_end signal // for informing we can read out in clk_cp clock domain. And make sure // there is not any datain_en coming in the read out phase. input pkt_end; // based on clk_vd;
output dataout_valid; output [7:0] dataout;
reg [4:0] wptr; // based on clk_vd reg [4:0] rptr; // based on clk_cp reg [7:0] mem [4:0]; always @(negedge vd_rst_n or posedge clk_vd) begin if(~vd_rst_n) begin wptr