Asynchronous design

Hi, I am designing a peripheral interface IO chip which is also the Intel i82C55 chip. THe problem I have is I want to change a interrupt signal INTR to '1' at the rising edge of a strobe input (STB) and then later change INTR to '0' when the read signal (RD) arrives (at the rising edge of RD). My VHDL code is

handshaking: process(STB, RD) is begin if rising_edge(STB) then INTR

Reply to
Chintan
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Code up an RS latch?

INTR = ~(RD | Q); // I think I have Q = ~(STB | INTR); // this right

That way you are at least making your latch out of purely combinatorial elements, and aren't depending on the chip being able to detect the rising edges of your strobe and read pulses.

I'd be inclined to catch the strobe and read pulses, synchronize them with my internal clock, and have a state machine that implements the above logic. The biggest drawback you'll have then is that the INTR line will go low a bit after the read goes high, but unless your logic is being clocked way slower than the processor you should be OK.

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Tim Wescott
Wescott Design Services
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Reply to
Tim Wescott

Thanks Tim..appreciate your help...but I am having problems coding the SR latch in VHDL. You think you can help me out with that..

Thanks again

Reply to
Chintan

A pure RS latch (of the NOR variety) follows (Verilog)

module RS (A,B,Q,nQ);

input A; input B; output Q; output nQ;

wire Qinternal; wire nQinternal;

assign Q = Qinternal; assign nQ = nQinternal;

assign nQinternal = !(A | Qinternal); assign Qinternal = !(B | nQinternal);

endmodule

The truth table is:

A B Q nQ

0 0 P nP 1 0 1 0 0 1 0 1 1 1 0 0 (F)

Where P is the Previous state (no change) F is forbidden (you should catch it somehow)

Note that this is a direct model of a NOR gate RS latch.

Cheers

PeteS

Reply to
PeteS

and here's the functional model

module RSfunctional (A,B,Q,nQ, RST);

input A; input B; output Q; output nQ;

always @ (A or B or RST) begin if(RST) begin Q = 0; nQ = 1; end else if(A & !B & !RST) begin Q = 1; nQ = 0; end else if(!A & B & !RST) begin Q = 0; nQ = 1; end end

endmodule

with the advantage of ignoring the forbidden state and the no change state. You could set a constraint (or code) to force nQ to start high instead of using a reset signal.

I have included the !RST statements for clarity only.

Cheers

PeteS

Reply to
PeteS

Chintan

One simple way of encoding this is to use one of the signals as clock the other as an asynchronous reset as follows

if STB = '0' then INTR I am designing a peripheral interface IO chip which is also the Intel

Reply to
John Adair

Another way to do this (I've used it successfully) is to resync the signal

for instance

reg EXT_INT; // from the external interrupt pin reg INT_INT; // a synchronised version of that signal reg INT_RD; // Synchronised internal read signal ....

always @ (posedge clk) begin EXT_INT

Reply to
PeteS

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