Hello all,
I have a microcontroller running at 40 MHz that performs asynchronous bus transfers, and I have an FPGA running at 100 MHz. With talk of metastability and all I would conclude that sending some of the control signals through flip flops (say 2 levels) would eliminate any metastability. The question then becomes how do I keep the bus transfers short enough without incurring significant delays between registering a read command (for example) and then responding to it and placing the data on the bus to be read. This would have
2 clock cycles to eliminate the metastability on the read signal (and address lines if I want to worry about metastability with those lines) and then at least one more for the data to be placed on the bus, a total of three clock cycles. That is too much time to get the data on bus (if I'm trying to keep the bus cycles short). I would appreciate some advice on how others have handled transferring data between an asynchronous device and an FPGA.Would it not be acceptable to make an asynchronous interface block for the FPGA, and then pull it into the synchronous world inside the chip? This seems to go against the metastability thoughts that I've come across.
Any and all comments would be appreciated..
Thanks,
Jason