Asynch. signal

Hi,

I have interfaced the eight bit data bus and the clock signal of the USB device to the CPLD. The USB device stores 8 bit in the CPLD'S buffer at every clcok cycle . I need to store 32 bits in the buffer then serial out those bits. I can not serial out the data on the USB clock because when there is not data there is no clock thats how the USB device works. So, I planned to have another clock which serial out the data. But I am worried about the communication between the the two processes. Because when the buffer is full, it will generate the signal to the serial out process and that Flag signal might be missed. So can somebody advice me with a solution.

Thanks Regards John

Add a flip flop clocked by the usb clock domain that toggles (changes to opposite state) each time the usb data is written to the register. Then synchronize the toggle signal to your local clock domain by passing it through a flip-flop or two clocked by the local cloc domain. Then after the signal is syncrhonized, delay it one more clock, and use the exclusive or of that signal to clock enable a second rank register. The xor will produce a 1 clock wide pulse in your local clock domain that happens well after the data is available at the outputs of the first rank register. This is reliable as long as the local clock domain is clocked several times between each usb transfer. In the case of your shift register, that clock enable can be the load pulse to your shift register. it would look something like this:

Process(usb_clk) begin if rising_edge(usb_clk) then if we='1' then capture_register

So does the USB provide some signal that asserts once it is done tranferring data? Is it a pulse or true handshaking? Meaning, does the USB process assert a "done" signal until it sees a "ack done" signal from the serial out process? Does this happen in 32-bit increments ONLY? Are you assured that the USB does not try to send more data while you are shifting out the data serially? Or are there measures to take care of that? I am just reading in to what you wrote. I may not understand it correctly.

I am not that familiar with CPLD's and what you can do with them (their limitations)...sorry. I am more of the FPGA camp.

But if you provide more details, I think it can be hashed out.

Hi,

Thanks for the reply! But do not have "we" signal or input pin available. Please advice.

John

Surely you have something that indicates the usb data is valid, no?

If not, then just clock the whole thing at your local clock.

Hi,

yes, I do not have any signal form USB device to tell me that the data is valid or d> john wrote:

This doesn't make any sense. What device are you talking about ? I think you're missing something in your reading of the datasheet. Is the clock you mention the output of the usb clock recovery ? Are we talking about FS or HS USB here ? Some more information would be helpful to help you :-|

Ok, so the USB "clock" is really a data strobe.

Use that strobe signal to write the eight bit data line into a register and also to toggle an additional bit. You might have to use falling_edge instead, depending on which is the active edge.

process(strobe) begin if rising_edge(strobe) then usb_register