async. load line on shift register

I just spend days debugging an issue and though I fixed the problem, I don't see why it was an issue in the first place. Here is my shift register that I implemented on a Lattice LC4256V:

library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_arith.all; use IEEE.STD_LOGIC_unsigned.all;

entity shifter11 is port( clk:in std_logic; rst:in std_logic; data_in:in std_logic_vector(10 downto 0); shift_load_select:in std_logic; shift_in:in std_logic; data_out:out std_logic); end shifter11;

architecture bhv of shifter11 is signal data_latched: std_logic_vector(10 downto 0); begin process(clk,rst) begin if(rst='0') then data_latched