I have tried to instantiate the Asynchronous FIFO core (v6) from Coregen, and it's been giving me trouble. First, I can't get it to produce a FIFO using distributed RAM (I wanted a 31-deep FIFO). When I try, it tells me there is a block RAM in the usage summary. If I try to open the core again after it's generated, it sometimes just beeps and exits (no error messages at all), sometimes it goes into the coregen wizard with "Block RAM" selected and the FIFO depth some enormous value like 65536.
I am using ISE 6.3.03i, with the latest IP core updates installed.
If it was a synch. FIFO, I have my own core, but I need an Async FIFO to cross clock domains and I dont want to waste a BRAM site.
-Jim