No, I'm pointing out that your argument on costs doesn't necessarily stack up.
The reason why the options are so constrained, and why this doesn't exist as a popular product, is that not many Linux-capable CPUs have an external bus interface or a high bandwidth GPIO interface. Basically you're stuck with PCIe (which ups the FPGA cost a lot) or things with SPI to try and squeeze enough bandwidth out.
Things like the OMAP PRUs might do it, but I'm not sure what useful bandwidth you can get at the end of the day (since there's no help with the wire protocol, you have to do it all in software).
That leaves the options as roughly:
- Zynq/Intel SoC parts (on-chip FPGA)
- some Microsemi parts with a hard Cortex M (not Linux capable)
- OMAP PRU
- I think I saw a single iMX part with an external bus interface, but it was slow
- an FPGA with a soft core running Linux (Microblaze, NIOS-II, RISC-V of some kind). These have a myriad of sharp edges, as the core/kernel/drivers/compiler/distro is often not very polished
- PCIe
- a few parts (eg Cavium ThunderX) which expose the cache coherency protocol externally. You'd be very much on your own here.
Another horrible idea: write a NAND flash interface for the FPGA and use that to emulate an external bus interface. You'd have to disentangle whatever cleverness the CPU's NAND controller tries to do, but in principle the bandwidth is there.
Basically you've boxed yourself into a corner here, so all these options are not very appealing.
Theo