You can't avoid 100% of all async reset flops but you can easily do the
99.999% where sync will give you a smaller, faster design and your design is still a black box equivalent to using the async reset.With xilinx parts every flop with an async reset wastes 1 lut over a sync reset. In asic design every async reset flop doubles the number of endpoints needing timing closure from 1 to 2. If you do a really lousy job in designing your reset distribution then these async paths could become critical paths and start taking routing resources away from your other more important paths.
Async resets on flops are nothing but trouble.
John
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