AREA_GROUP Map Error

I have a design that instantiates four copies of a module and I am using Xilinx's AREA_GROUP constraint to partition each instantiation into its own

1/8th sector of the FPGA. I ran across a few problems. One, how do I convey these constraints to Synplify (v8.8) for my final implementation run? I tried xc_area_group constraints on each top-level instance name, but either my format is wrong or it just doesn't feel the need to respect them, because they get placed in rectangular fashion around the center of the FPGA. On a similar note, would it be better to use RLOC constraints for what I am trying to do instead?

My main problem is in ISE 9.1.03 when attempting to Map the design. I get the error message below at phase 1.1. I also listed the contents of my .ucf file below. I don'y get this error when "Resource Sharing" is turned on. I still get the error though even when "Use RLOC" is off. Any suggestions?

ERROR:Place:293 - The following 13 components are required to be placed in a specific relative placement form. The required relative coordinates in the RPM grid (that can be seen in the FPGA Editor) are shown in brackets next to the component names. Due to placement constraints it is impossible to place the components in the required form. LUT FPU1/Madd_tmp_expAB_addsub0001_cy(1) (0, 0) LUT FPU1/Madd_tmp_expAB_addsub0001_cy(1) (0, 0) FF FPU1/Madd_tmp_expAB_addsub0001_cy(1) (0, 0) LUT FPU1/Madd_tmp_expAB_addsub0001_cy(3) (0, 1) LUT FPU1/Madd_tmp_expAB_addsub0001_cy(3) (0, 1) LUT FPU1/Madd_tmp_expAB_addsub0001_cy(5) (0, 2) LUT FPU1/Madd_tmp_expAB_addsub0001_cy(5) (0, 2) LUT FPU1/Madd_tmp_expAB_addsub0001_cy(7) (0, 3) LUT FPU1/Madd_tmp_expAB_addsub0001_cy(7) (0, 3) LUT N14610 (0, 4) LUT N14610 (0, 4) LUT FPU1/Madd_tmp_expAB_addsub0001_cy(8) (0, 5) FF FPU1/Madd_tmp_expAB_addsub0001_cy(8) (0, 5)

NET "clk" TNM_NET = "clk"; TIMESPEC "TS_clk" = PERIOD "clk" 40 ns HIGH 50 %;

INST "FPU1/*" AREA_GROUP = FPU1Group; AREA_GROUP "FPU1Group" RANGE = SLICE_X0Y0:SLICE_X51Y63; AREA_GROUP "FPU1Group" RANGE = RAMB16_X0Y0:RAMB16_X1Y7; AREA_GROUP "FPU1Group" GROUP = CLOSED; AREA_GROUP "FPU1Group" PLACE = CLOSED; AREA_GROUP "FPU1Group" COMPRESSION = 0;

INST "FPU2/*" AREA_GROUP = FPU2Group; AREA_GROUP "FPU2Group" RANGE = SLICE_X0Y64:SLICE_X51Y127; AREA_GROUP "FPU2Group" RANGE = RAMB16_X0Y8:RAMB16_X1Y15; AREA_GROUP "FPU2Group" GROUP = CLOSED; AREA_GROUP "FPU2Group" PLACE = CLOSED; AREA_GROUP "FPU2Group" COMPRESSION = 0;

INST "FPU3/*" AREA_GROUP = FPU3Group; AREA_GROUP "FPU3Group" RANGE = SLICE_X0Y128:SLICE_X51Y191; AREA_GROUP "FPU3Group" RANGE = RAMB16_X0Y16:RAMB16_X1Y23; AREA_GROUP "FPU3Group" GROUP = CLOSED; AREA_GROUP "FPU3Group" PLACE = CLOSED; AREA_GROUP "FPU3Group" COMPRESSION = 0;

INST "FPU4/*" AREA_GROUP = FPU4Group; AREA_GROUP "FPU4Group" RANGE = SLICE_X0Y192:SLICE_X51Y255; AREA_GROUP "FPU4Group" RANGE = RAMB16_X0Y24:RAMB16_X1Y31; AREA_GROUP "FPU4Group" GROUP = CLOSED; AREA_GROUP "FPU4Group" PLACE = CLOSED; AREA_GROUP "FPU4Group" COMPRESSION = 0;

---Matthew Hicks

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Matthew Hicks
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The error in ISE seemed to be also fixed by removing the "Perform timing driven packing and placement" option. My guess is that the special carry structures infered during synthesis came with special packing requirements (only for timing driven packing/placement) that were violated if resources couldn't be shared. I'm still awaiting further insight into this and my other problems.

---Matthew Hicks

Reply to
Matthew Hicks

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