Area Constraints in Xilinx

snipped-for-privacy@gmail.com schrieb:

gosh, you are heavy coder! well for the future there is one good advice:

LOOP: wrote 2 lines of code, hit "View Technology Schematic" and verify that the synthesis does something useful. Goto LOOP

this will make sure you arent facing this kind of surprises.

now you have to start from the bottom and look at lower modules what they produce and work up to the toplevel unit to see where the logic and rams really are consumed.

Antti

Fire up the Floorplanner after translate and it will give you a breakdown of where resources are used if you have maintained hierarchy. Synthesis report can also give some clues too.

John Adair Enterpo> snipped-for-privacy@gmail.com schrieb:

To do much useful in 500 lines of code and have that resource utilization as the output, my guess is that you are using a few IP cores which take up those resources.

---Matthew Hicks

I'm curious which Xilinx device and package you're targeting. I didn't do an exhasutive search, but I didn't see any Virtex-II, or Spartan (2, 3, 3E) parts with the resources listed above.

Rob

Sorry, I assumed that you used the primitives to instantiate the BRAM or wrote it so the synthesis engine would infer it (how I like to do it). I was guessing that you had other heavy weight cores that weren't just instantiating built-in primitives. An example would be a FIFO.

---Matthew Hicks

I think that you must have a basic misunderstanding with your code. I can only give you the obvious advice :

- Think hardware. Every signal or process (or whatever) you write must correspond to a basic 'physical' structure you have in mind (or on paper).

- Try to synthetize and check the smallest possible part and try to isolate the ofending code.

- If everything else fails, put your code on a webpage, and some of the experts here may spot the problem for you.

Best regards

Josep Duran