Hello, FPGA friends,
I'm trying to implement a simple clock bypassing on my Virtex-II 6000 with an FF1152 board. My ISE is version 5.2.03i. In the beginning I could do a trivial bypassing using Virtex 2000E with a BG560 board:
input clk; output out_clk; wire out_clk;
out_clk=clk;
But on my Virtex-II 6000 it didn't work. It's fine since that I could try FDDRRSE to accomplish the same task. My code evolved as:
input clk; output out_clk; wire out_clk;
FDDRRSE fddrrse_0 ( .Q (out_clk), .C0 (clk), .C1 (~clk), .CE (1'b1), .D0 (1'b1), .D1 (1'b0), .R (1'b0), .S (1'b0) );
After browsing the old messages of this news group, I didn't know why the above code failed again. The output port just stuck at logic 0, and it looked like that fddrrse_0 was power-up and did nothing. Then I tried to use Xilinx floorplanner to see what FDDRRSE was. Here I found it not being floorplanned. Well, maybe it was too trivial to be floorplanned. Hence I used Xilinx FPGA editor to see what the connections were like. However, besides my fddrrse_0, I didn't find any nets other than the I/O port between the inferred input and output buffers and some VCCs. And it looked like clk --> clk_IBUFG --> out_clk was the whole route.
I believe I might have missed something there such that neither could I bypass clock signals correctly nor could I understand what Xilinx floorplanner and FPGA editor told me.
Please give me some suggestion to understand even some parts of this problem. Thank you :-)
Regards, Merlin