architecture

hi again, I need this because I must know if the core -when designed- was optimazed for area or for delay .

Depends who wore the core doesn't it ? If its the Xilinx core then it is optimised for the architecture you tell core generator to generate. Xilinx cores tend to be hand fitted to be the most optimal solution for the device.

Simon

For generating the core I used coregenerator of Xilinx. I even searched for more references in their Datasheet and there is nothing. I generate this core (32 bits-adder unregistred) in order to design an other 32 bits adder with 3 input ports, then I must optimize it.

nezhate schrieb:

In xilinx FPGAs there aren't really any architecture options for single cycle adders. The special carry chain hardware is so much faster per bit than LUT-logic that the break even point between carry ripple adders and more sophisticated adder architectures happens at relativly large bit counts, if ever.

Kolja Sulimma