Anyone routing signals between balls in FBGA?

Altera's app note "Designing with FineLine BGA Packages" indicates that it is ok to route one (or even two!) signals between 1.0mm balls.

My question is if anyone is actually doing this? What is the effect on yield?

Does Altera or anyone else offer a proven board or set of gerbers demonstrating this routing technique?

Thanks, Ken

Reply to
Kenneth Land
Loading thread data ...

I think so. Xilinx recommanded escape pattern uses 1 line between balls.

Sylvain Munaut

Reply to
Sylvain Munaut

I think the real question is how on earth can you AVOID routing tracks between a BGA pads? I can't think of a single board that I've ever seen with BGA devices with no traks between the pads.

Reply to
Arash Salarian

The Pulsonix software I use has a Xilinx BGA part in the library with breakout tracks which are routed between the balls. They are 5 mil width, as are the tracks on the inner layers between the vias, but there are plenty of companies who can handle that.

Leon

Leon

Reply to
Leon Heller

Kenneth, Yes I do this. I get two tracks between the outer balls on the surface layer. Our PCB fab house's standard process is 4 mil tracks with 4 mil gaps. For BGAs the land size for the ball should have a diameter of half the ball pitch. The ball pitch is 1mm or 39.37 mils. So, the land diameter should be

19.69 mils, with a gap between adjacent lands of the same, 19.69mils. To get two 4 mil tracks between, with 4 mil gaps needs 20 mils. Gap track gap track gap! If you look very very closely at my boards, you'll find the outer ring of ball lands are slightly oval, to get the gap between them up from 19.69 to 20 mils! I kept the same area for the ball lands by extending the other axis a fraction, but I don't think it was really necessary. So, using this, the outer 3 rows of balls route out with no vias. Cheers, Syms.

Reply to
Symon

gaps.

ball

be

get

track

ring

this,

Nice detail. With our boards - given the tolerance slop from plating up the outside layers - we keep our 4-mil (or 0.1mm) lines and spaces on the inside layers allowing 2 signals between vias while keeping looser line width/spacing rules on the outside layers which gives us single lines between balls or vias.

No yield problems if the board house works with those dimensions *and* you use a proper solder mask. I'd hate to think of someone attempting to mount a FBGA on a board without a solder mask. Yikes!

Reply to
John_H

If you don't mind reading something from the other side of the fence, check the XAPP157 on xilinx web ;-)

Also of interest is a paper from motorola, named "PBGAPRES.pdf" probably you can still find it at freescale.

I also remember reading something on TIs WEB, as they also use BGA packages with 0.8 mm spacing.

Good luck ...

P.S. And check your gerber files with a goo editor, before you give them to the pcb house. Specially the solder stop and solder paste masks. My first experience with BGA pretty much was for the trash bin ;-)

Reply to
E.S.

My first experience with BGA, I stuck the vias in the pads. The company that was installing the chips for me said it would be fine. They got one to work out of about 20 tries, after which I gave up and did some research and redid the board the right way.

5/5 spacing is as low as I've gone, never had to try 4/4 with 2 tracks through yet. Sounds like fun.
Reply to
Chris

that was installing the chips for me said it would be fine. They got one to work out of about 20 tries, after which I gave up and did some research and redid the board the right way.

We've put vias on the pads with two big bga designs - one using a Motorola MPC561 with around 360 balls, and one using a Stratix with 1040 balls. Both designs worked perfectly first time (well, the Stratix board doesn't work fully yet - but not because of dodgy connections!), and we've made several dozens of the MPC card with no failures. Putting a hole in these pads is outside the spec's for our pcb supplier (they are 18 mil pads with a 9.8 mil hole in the middle), but they took it as a challenge. They filled the holes with varnish - without that, there would be the risk that the solder would flow through the hole during soldering and leave a bad joint.

To be honest, I can't see how we could have routed the card without doing this. Putting vias between the pads takes up more space and needs tighter clearances, especially on the top layer.

through yet. Sounds like fun.

Most of our Stratix board is 6/6, but I used 4/4 for the area around the FPGA on the top and bottom layers only (where it is easier to check!) to get denser routing where I needed it the most.

Reply to
David Brown

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.