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Another simple DCM question

I have a design where I want to have 2 DCMs, each with there own clock source come up with some known phase. The two clock sources have a fixed phase relationship. I routed a single reset signal to both DCMs. If the DCMs are a 1:1 clock ratio, no problem. However, if they are 2:1 (CLKIN_DIVIDE_BY_2 => TRUE), then often out of reset I see the phase of the output clocks will change. Even though the reset is async, I sync'ed it to each of the DCM's input clocks. This seems to have an effect and does help. The part is a Virtex 4. I have not tried it on any other device.

Any ideas?

Reply to
lecroy7200
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1) Build a circuit to detect the phase relationship and re-reset one of the DCM's until they match the phase you want? 2) Don't use the CLKIN_DIVIDE_BY_2.
Reply to
Gabor

Or,

Use an inverted version of the clock to a BUFGMUX, and when it isn't right, switch the BUFGMUX to the other clock input.

Austin

Reply to
Austin Lesea

I think this takes the BUFGMUX out of the feedback loop and you would then lose your best phase relationship.

Normally a BUFGMUX (used as a BUFG) is connected from the CLK0 output of the DCM to the feedback pin to remove BUFG delay from the clock. You could use a second BUFGMUX on CLK0 and CLK180 outputs with a switch to select the one you want, but the routing delays to the two BUFGMUXes might have a small difference.

Reply to
Gabor

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