Announcement: Releasing LogicSim 3.3 and WaveProbe 1.1

I'd like to announce the release of LogicSim 3.3 and WaveProbe 1.0.

LogicSim is an affordable and user-friendly Verilog simulator for ASIC and FPGA design verification. It offers a powerful and easy-to-use graphical user interface that lets you quickly simulate your Verilog designs. Please check out the release notes for more info.

WaveProbe is a waveform viewer useful for examining the output of various logic simulators (like LogicSim, ModelSim, VCS). It offers a powerful and easy-to-use graphical user interface that lets you quickly analyze and debug your waveform files. Please check out the release notes for more info.

For existing customers, please receive your free upgrade here, just enter your purchase time email address and an activation key will be sent to you immediately.

I'd like to thank those who continue submitting bugs and feedbacks. Without them, we would not be able to improve our software. Thanks for being our valuable customers and users.