Pasacco, you are mixing up two things: Renz' rule, and real FPGAs A real FPGA family does not span a 100-to-one size ratio. Usually just
10-to-1. In Xilinx FPGAs, the area is roughly proportional to the number of CLBs or Slices or LUTs, pick your preferred measurement. This picture gets more complex due to the large number of non-CLB elements (BRAMs, I/O, multipliers, CPUs etc.) that also populate the FPGA. And play a very important role in making the FPGA fast, efficient, and competitive. I assume yours is a theoretical discussion... Peter Alfke
First of all: Peters observation is correct. While even for a dynamic of 10:1 you should have more wires per routing channel, you do not see much of that in real fpgas for practical reason. A regular structure is simpler to design, test, write software for, etc. So I expect Xilinx to design the routing based on the requirements of the large parts. Maybe a little on the short side. This means that the small devices have more wires than needed. But as yield is an exponential function of size the economic impact of extra wires is not as important for smaller devices.
However in some families you seed routing structures that only appear for larger devices. For example in Coolrunner the macrocells are grouped. The smallest device has only one group (dont remember the name of the group in Xilinx Lingo) with routing in the group. The next device has two groups, plus routing between them.
Some families of some vendors increase the number of wires in all routing channels for larger devices or add an additional long distance routing ressource in the center of the FPGA for larger devices.
Were you see rents rule > For example, suppose :
Yes, were roughly. The better formulation is: A design in the large device is expected to use about that much more wires than a typical design in a large device. The manufacturer might chose to deviate from that for other reasons. Also, this is a typical value. Designs vary. A smith-waterman pattern matcher has a rent exponent of
0, so does an SRAM.
What is the maximum distance in a chip with 100 LUTs laid out as a square? What is the maximum distance in a chip with 10000 LUTs laid out as a square?
This is the result of Rents expirments in the 60ies. They have been verified many times in later experiments, also for FPGAs. Actually Rent counted terminals, but the wires are roughly proportional to terminals because must wires have a very low number of terminals on them.
Now I better understand. Number of wires grows faster than number of logic, though the "growth rate" in state-of-the-art FPGA device is not that high. Thank you for providing a good example.
A good source with some reference to Rent's rule may be: @techreport{ dehon96reconfigurable, author = "Andre' DeHon", title = "Reconfigurable Architectures for General-Purpose Computing", number = "AITR-1586", pages = "368", year = "1996", url = "citeseer.ist.psu.edu/dehon96reconfigurable.html" }
These things are general observations and tendencies. Much like Moore's law, there is no hard science behind them: they just turn out that way due to engineering/marketing/economic/etc. reasons.
For FPGAs, routing resources are simply scaled to compromise between the routability and performance targets requested by customers, manufacturability, engineering mindset, company policies, marketing spin, expected market developments and countless other variables.
If synthesis tools reported unused wires, I bet many FPGA customers would start complaining about the cost of having so much "dead copper" even in fully routed FPGAs... I bet current designs use far less than 25% of all routing and this figure actually sinks as devices scale up.
ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here.
All logos and trade names are the property of their respective owners.