It happens in a Virtex-E
There's a 1M cycles test pattern on a 10 bit data bus with an ENABLE signal (high for 1 M cycles) indicates data valid. The pattern is clocked at 40 MHZ (0_degree)
The data & enable is then fed into an accumulator with input registered. The ACC does the sum for exact 1M cycles. The ACC and its input register is clocked with the 90 degree phase shift
The 0_degree and 90_degree clocks are DLL outputs (please dont ask why it has to cross to the 90 degree). DLL has been locked long time before ACC start (enbale high)
PAR post timing well passes the 40 MHz constraint
Here's what happens
The accumulator once a while (about 1 out of 100) gives a random wrong result. If I put another 90 degree clocked register before the ACC, it fixes the problem. it seems not the setup time violation since 25/4 = 6.25ns is much longer than the requirement