Alternative for Mentor''s HDL Designer

Impossible in replaying to the newsthread "ModelSim Designer", I'd like to place my quastion here:

Is the a free tool to draw state machine with and handle signals in an graphical environment?

I agree to the former article where it has been said, that most design engineers might not use HDl-Designer, but I found it very convenient for keep the overwiev in design with a large amonunt of signal interactions.

Reply to
homoalteraiensis
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Xilinx ISE comes with StateCad, which produces truly awful to read HDL, but otherwise works. Since the tool produces straight VHDL/Verilog, you could probably take the output and port it to another target, though the license may prohibit that now that Xilinx owns it.

Reply to
radarman

homoalteraiensis schrieb:

Hi, you can use XFIG to draw your State Diagramm and convert it with brusey20 to VHDL.

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have a nice synthesis Eilert

Reply to
backhus

VHDL.

that's a very nice tool!

Martin

Reply to
Martin Schoeberl

VHDL.

mmh, I tried to run it under Cygwin and under Linux. Got on both segementation faults or application errors with the provided examples. A nice idea, but didn't work.

Martin

Reply to
Martin Schoeberl

Hi, Mentor's HDL Designer has many functions. But I really do not see any requirement to use a tool to generate a state machine (I have tested the tools from mentor and Xilinx ISE). Directly writing the code in a single always block is already very clear and easy. By using such tools usually cost more time. Many other functions in the HDL Designer are very useful. As a large company, Mentor's products indeed cover a very wide area, but at least in some cases, the free tools from Topweaver family are much more powerful.

1, Comparing TME with HDL Designer's Tabular IO, TME shows better performance in parameter/generic, dynamical adjustment of HDL code format, secure code synchronization, complex HDL code template and launch speed. 2, Like ISE, QUARTUS, ActiveHDL and other tools, HDL Designer's module integration function is based on traditional schematic method, which is hardly used in large projects. You can see these tools' demo all using only a few modules and wires. Topweaver can easily deal with hundreds of ports. A quick demo from
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can show how to fulfill the integration work within a few minutes. If you can use any other tool to get the same performance, please let me know. Now the new version of Topweaver is in the final test.
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Reply to
topweaver

I agree - which is why I only produce state machines in HDL Designer that need to be documented, or are designed by someone else. The tool does a nice job producing pretty graphics, and reasonable HDL. The documentation facility alone makes it worthwhile for those "committee" jobs. While you could use Visio, or some other graphics package, HDL Designer allows you to produce exactly what you drew - so the documentation is immediately linked with the actual design - eliminating documentation errors.

However, for the vast majority of my state machines, I just write them out without any tools (other than UltraEdit).

Reply to
radarman

The quartus hdl/state machine viewer works the other way around. It picks state machines out of vhdl or verilog code and can print them like this:

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-- Mike Treseler

Reply to
Mike Treseler

Documentation ist the point! For certain applications, a detailed docu has to be deliverered too, no matter how fast text based coding had been or might have been.

I once had a project with several hundred states, hard to keep an overview when just dealing with text based signal handling, and almost impossible to work with 2-3 persons at it the same time.

Mike Treseler wrote:

Well, I know about this function but did not find it convenient. States are placed in linear order and obviously it is not possible to rearange this or use this diagram for further input.

Reply to
homoalteraiensis

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