Hi, Who could enlighten me with the followings:
I need to interface a SERDES transciever from a VIRTEX5 FPGA with a STRATIX II IO. Things would be easiest if I'll have a Stratix II GX instead of Stratix II, but the GX FPGA has no HARDCOPY II structured Altera ASIC corespondent, so I can't use a GX because of finacial reasons (and huge ball numbers, improper for this design).
How could I get an equivalent of 3Gbps SERDES transciever (like GX has) using only high speed differential IO available in STRATIX II?
thank you, Vasile