Altera why so QUIET !?

Hi Antti,

Glad to see you back!

Personally, while not directly working for Altera, I'm pretty occupied with a six-week old son who unfortunately has inherited my aversion to sleep (instead of my wife's addiction to it) ;-)

I guess Altera's a bit quiet because there's no huge news - the Virtex4 vs Stratix2 war is now fought in the field instead of the press, Quartus II version 5.1 isn't out yet (but soon, my friend, soon) and neither are Stratix2GX and Hardcopy2 (but which will give FaultyBits - er - EasyPath a run for its money very soon).

Best regards,

Ben

Ben,

Yes, it is nice to see Antti posting again.

By the way, if Altera doesn't use "faulty bits" why do you have:

1 6,759,871 Line segmentation in programmable logic devices having redundancy circuitry 2 6,600,337 Line segmentation in programmable logic devices having redundancy circuitry 3 6,337,578 Redundancy circuitry for programmable logic devices with interleaved input circuits 4 6,222,382 Redundancy circuitry for programmable logic devices with interleaved input circuits 5 6,166,559 Redundancy circuitry for logic circuits 6 6,107,820 Redundancy circuitry for programmable logic devices with interleaved input circuits 7 6,091,258 Redundancy circuitry for logic circuits 8 6,034,536 Redundancy circuitry for logic circuits 9 5,498,975 Implementation of redundancy on a programmable logic device

9 Patents (plus) for them?

Your use of laser frapped fuses to replace bad columns is identical to EasyPath (we just avoid the defects, the same as you).

'HardcopyTo' really does live up to its name: not pin compatible, and a custom ASIC in every (bad) sense of the word.

Meanwhile, 'EasyPath' remains easy, and now includes the standard option of being able to change the logic (LUTs may be reprogrammed) or change the IO (strength).

Every try to ECO an ASIC?

With EasyPath, it is still just bits.

Austin

Hi Austin,

First of all, thanks for having been polite and courteous to everyone while I was on paternity leave.

Second, to reiterate, I do _not_ work for Altera. I did, but I don't, and haven't done so for several years. Thus, any reference to Altera with 'you' when replying to my stuff is wrong.

Yep, and for you too. Not sure whether you actually had to use Altera's cross-licensed patents to make EasyPath see the light of day, but it surely must have saved on attorney fees, and $DEITY knows all of us should avoid feeding those critters.

Those patent cross-licensing deals are good, aren't they?

To be honest, I always understood that EasyPath devices were carefully selected defective parts where the defect happened not to interfere with the specific user's design. Thanks for clarifying this. You just can't trust Marketing people these days.

Just like with an FPGA... Ok, but now I'm thoroughly confused. Can you tell me, on a hardware level, what is the difference between your standard XC4Vxxx offering and its accompanying EasyPath device?

Yep, and it's something best avoided. I FIBbed a few dies. Not fun, and I was a lucky bastard for getting two of the bloody things to work that way. Then it was bow-in-shame time for requesting a new mask from the boss...

Best regards,

Ben

Ben,

See below,

-snip-

Congratulations.

I will remember that in future.

We do not use any laser, or other non-volatile methods to improve, or increase die yield (yet).

Not sure whether you actually had to use Altera's

Nope.

but it surely

Altera's patent portfolio is quite respectable. So is ours. Due to the last legal settlement, I can not comment on any of it.

Again, no comment. I am all for avoiding those 'critters' as well...

Who at Xilinx every represented EasyPath as any other than what you described above? I understand Altera tells everyone EasyPath are "defective" parts. They also fail to mention that ALL of their parts use redundancy to repair defective portions of their FPGAs. At least our non-EasyPath FPGAs really have no defects whatsoever.

EasyPath is tested to the customer's pattern, and represents an extremely high test coverage for their specific application.

One advantage of EasyPath is that our method of testing provides a much higher quality part than ASIC testing is capable of.

Absolutely nothing at all.

No difference (in silicon).

The EasyPath component is just tested (and marked) for a specific bitstream (or two).

A customer can have a bistream for in-house manufacturing test, and another one for the application, or any two of their choice as an option.

Try that with an ASIC sometimes!

Then you can imagine what fun it is to do backside fib'ing of flip chip die. But, one advantage of "hardtocopy" is that Altera has to do the fib'ing when something doesn't work (not the customer).

We just change bits and the customer keeps shipping, uninterrupted.

This was my understanding as well. I think most people who take the time to read about it come to this conclusion.

Well, to be honest, going from the marketing materials alone, I wasn't quite sure if it was a new flavor of peanut butter or a boiled cabbage accelerator. But Xilinx's marketing department isn't really any worse than any other silicon valley company in that regard. ;)

Interesting, I didn't know that.

Er, really? I thought you had to pay extra for the 100% tested ones. Does Xilinx really test every net on every chip for (say) stuck-at faults before shipping?

- a

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PGP/GPG: 5C9F F366 C9CF 2145 E770  B1B8 EFB1 462D A146 C380

Hi Austin,

I unfortunately don't get to talk to Xilinx people very often nowadays, which is a bit of a pity because I used to get along well with the whole Xilinx FAE team in Belgium - including Marc Defossez.

Well, they were presented to me as 'possibly partially defective parts, but happening to work OK with the specific customer design'.

Not quite true. When the EP20K1500E and its slightly less bulky brethren came out Altera quite proudly presented the redundancy as a yield improvement technique. The redundancy 'feature' was also present in Stratix customer presentations. I don't remember about Stratix II presentations though.

Oh, once Altera's repair department is done with a die, so does a Stratix (II), which is 100% tested as well.

So, can I then summarize that EasyPath is basically a standard Virtex II/4 but with less time on the testbed (only the cells and routing used by the customer are tested) in order to reduce cost?

Best regards,

Ben

Adam,

The "stuck at fault" testing is extremely high: we carefully examine test patterns for their IC design shcematic coverage.

Even the generic FPGA flow test coverage is much better than an ASIC.

Austin

Ben,

-snip-

There is a basic 1's, 0's, shorts, leakage, etc test done to all parts, EasyPath or no.

And then, for EasyPath, only those features used by the customer are tested (with the addition of any LUT pattern for the CLBs they use, and any IO strength for th IOB standard they use, which allows for the two most common ECO requests we got after we shipped). The difference in test time between as close as we can get to 100% testing for any possible use, and as close as we can get to 100% testing for one use is SIGNIFICANT.

As well, the test yield to one test program is also SIGNIFICANTLY HIGHER than for many thousands of test programs (which is potentially what it takes to have an acceptable AQL).

Better Yield + Shorter Time = Lower Cost to Xilinx, which means Lower Prices to customer.

Austin

Ben -

Although I haven't used Xilinx' EasyPath product, it makes a fair amount of sense. I've used V2Pro parts for a while, but I don't care about or use the PowerPC processor I get in the the part. EasyPath would let me get cheaper parts in volume for 2 reasons -

a) Xilinx doesn't even have to test the PPC core in parts they would ship to me. They save dollars because of chip test time saving.

b) Xilinx could send me parts with dead PPC cores since I don't use that feature. I assume the PPC core takes a reasonable amount of silicon area, so it would have a reasonable chance of having a defect. Those 'dead' chips are currently lost revenue to Xilinx, the incremental cost to sell them to me is fairly low.

I don't know how the EasyPath cost compares to the Altera HardCopy2, but it sure makes sense that EasyPath could offer nice savings for the volume user and additional profit for Xilinx. A win-win situation.

John Providenza

I'm assuming it's mostly "better yield", though, right? I mean, Atmel's chips can 100% test themselves (they'll even give you the bitstream that does it), and I'd bet that the XC6200 could've (or probably even did).

Isn't the test time just a matter of "assembly line latency" rather than "assembly line throughput"? It shouldn't be like an ASIC where you need a separate, active device to test it and those devices are in short supply.

Forgive me if this sounds stupid. My knowledge gets pretty fuzzy down at the fabrication/process level.

- a

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PGP/GPG: 5C9F F366 C9CF 2145 E770  B1B8 EFB1 462D A146 C380

The point is, the easy path parts are not known defects, they are simply not tested as rigorously as the non-easy-path parts. Basically, they reduce the test program to test only what your bitstream actually uses in the design (and some testing of other unused logic, but not nearly as rigorous). The result is significantly reduced testing time and increased yield, which translates into a cost savings. What they guarantee that way is only that it will work with your bitstream. It could be a perfectly good part, or it could have a defect somewhere where it doesn't affect your design. No one knows, because no one tested it.

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Hi Austin,

Of course. The global die specs must be met.

Sounds quite reasonable. So, technologically there's nothing holding Altera back in investing in a few extra ("standard") device testers and, as an intermediate price-reduction step, doing same under the hereby trademarked name "Crippledie" (come to think of it, sounds great as the title of an ultra-violent FPS game taking place in a hospital or a leper colony too - I'll have a chat with my local EA Games marketing guy).

I can't imagine that only partially testing an ASIC is patentable - but then again, one-click-shopping is patentable as well according the USPTO so I wouldn't be surprised.

Then of course there's HardCopy2, which, like EasyPath, only needs to be tested with the user design _but also_ is a lot smaller in die size.

Thus:

Better Yield+Shorter Time+Smaller Area = Even Lower Cost to Altera, which means even Lower Prices to customer. No ECO and no last-minute changes though, I'll give you that.

Am I right?

Best regards,

Ben

Shorter time? Lower cost? For an ASIC conversion product versus an FPGA? Surely you jest, sir! So the mask set just magically creates itself and pays for itself now, or what?

-Ben-

Hi Ben Jones,

OK, ok, forgot about the NRE to create the wiring/config layers. Blushing here. Then again, as far as I know, the setting up of the EasyPath part's testing program isn't free either.

However, once actual HC2 production of a design has started, most definitely yes - most layers are pre-fabricated, so once a certain design batch needs to be produced, only the top few (2? 3?) metal layers need to be deposited, either from from stock wafers or straight in the production pipe.

Also, assuming the same number of wafer defects (it's the same process after all), given the smaller die, the yield will automatically be higher.

Best regards,

Ben

Ben,

-snip-

Except that 'EasyPath' has patents pending with a number of claims that would prevent Altera from having an EasyPath clone (without paying us for the rights to do so).

Imagine if you will a car company that makes a top of the line car, and sells it for a lot of money. Now emagine the same company establishing a different distributorship for a lower cost version of the similar car, less chrome, less power windows, etc. (but basically all the same subcomponents).

Happens all the time, doesn't it?

Jaguar/Volvo/Lincoln/Ford. Buick/Potiac/GMC/Chevy. Lexus/Toyota. ...

Yes, but ....

An ASIC is always going to be lower cost, only if the volume can overcome the NRE cost. Now if Altera is happy to eat a majority of the NRE, and have lower margins (which, by the way they announced last financial report), then the customer benefits (obviously).

But, for every change, the whole cost picture is thrown out, as the line stops until the new good parts can be delivered.

Since H2 is not even pin compatible with the S2, the pcb must be redesigned. In some cases (most) the signal integrity analysis of all IOs must be repeated. I have heard a case where the cost of the H2 is very high, as the package is very expensive (that the customer wants).

To go from flip chip, back to a cheap wirebond package may result in Signal Integrity issues that can not be solved!

(By the way, I will not even go into how the H2 is not even a logic equivalent to S2: there are features and components that are just different between the two!)

With EasyPath, you go from the working solution, to a less costly working solution with no redesign whatsover, and no risk at all.

Seems like a simple problem to me: choose H2 and have a potentially career limiting experience, or choose EasyPath and go home happy every night....

Austin

Hi Austin,

[snip]

FPGA's are often touted as high-cost (sorry, A, A, L and X are) risk-mitigating devices versus ASIC. EasyPath users would indeed be the types who find the risk/delay involved with saving money by going to any kind of ASIC completely unacceptable but are running enough volume to recover the NRE charge for Easypath.

HC2 is supposed to sit between standard cell and FPGA (much closer to standard cell, I'll give you), which should find some high-volume customers with fast time-to-market and pricing requirements that are too tight for EasyPath but are not comfortable with standard-cell risk and development time. If you're making a flat-panel TV, a single cent saved in item cost is easily recovered in NRE, signal integrity testing etc. Unfortunately these cents are also saved by using crappy connectors, bad crystals, flaky switches etc, but that's not the issue here. People in Purchasing do take these risks...

The markets for both solutions are different.

One sort-of compelling thing about HC2 on the engineering side, by the way is this: have you ever designed an ASIC from a nice and user-friendly GUI? With Quartus you can...

Oh, and I know someone who was fired for choosing IBM...

Best regards,

Ben